||(Error Checking/ Correcting Code) A method used to check the integrity of data stored in memory . ECC memory improves data integrity by detecting errors in memory and is more advanced than parity because it can detect both multiple-bit errors and single-bit errors (parity only detects single-bit errors). ECC is typically found in high-end PCs and file servers where data integrity is key.
An ECC scheme capability is partially determined by the sophistication of the "systematic code" employed. The systematic code is like a reference table that the memory system uses to determine whether or not the memory has returned the correct data. Every time data is stored in memory, this code is responsible for the generation of check bits which are stored along with the data. When the contents of a memory location is referenced, the ECC memory logic uses the check bit information and the data itself to generate a series of "syndrome bits". If these syndrome bits are all zeros, then the data is valid and operation continues. If any bits are ones, then the data has an error and the ECC memory logic isolates the errors and reports them in the operating system. In the case of a correctable error, the ECC memory scheme can detect single and double bit errors and correct single bit errors.
|EDO Parity RAM
||EDO Parity RAM offers the high performance of EDO memory and has built-in parity which greatly improves reliability. Ideal for high-end PCs and entry-level servers, EDO Parity modules are compatible with any system that accepts a standard 72-pin EDO module and are rapidly becoming the new standard on high-end systems.
||(Extended Data Out) EDO RAM is similar to FPM memory, a form of DRAM technology that shortens the read cycle between memory and CPU. but provides improved performance by keeping available data longer in memory. It eliminates much of the wait time by allowing the processor to access data during the refresh cycle. In other words, the computer can load data as it is searching for new information. EDO memory is generally 10 to 20% faster than FPM memory. A computer must support EDO memory in order to notice an increase in performance.
||(Enhanced Dynamic Random Access Memory)--a form of DRAM that boosts performance by placing a small complement of static RAM (SRAM) in each DRAM chip and using the SRAM as a cache. Also known as cached DRAM, or CDRAM.
||Electrically Erasable, PROgrammable, Read-Only Memory chip. EEPROMs differ from DRAMs in that the memory stays in even if electrical power is lost. Also, the memory can be erased and reprogrammed.
||(ECC on SIMM) A data-integrity checking technology designed by IBM that features ECC data-integrity checking built onto a SIMM.
||Erasable Programmable Read Only Memory
||Even parity and odd parity are two different parity protocols used to check the integrity of data stored in memory. A memory manufacturer can use either protocol in a memory product. Even parity adds an additional bit to every byte of data to make the total number of 1's in the segment even. When the byte passes to the CPU, the parity circuit checks the byte to be sure it is still even. If it is, the data is considered to be valid and the parity bit is removed from the byte. If instead it registers as odd, it is considered to be invalid and a parity error is generated.