|Sunday, May 28, 2017|
Clock Reference Board
Why the need for Clock Reference Board ?
1. Current industry practices do not provide a
method for ensuring module clock timing accuracy especially for PC100/PC133
SDRAM ,DDR,DDR2 & DDR3.:
2. 'PC100 or PC133-compliant' DIMMs, from major suppliers, may vary by greater than 1ns (10% of cycle time!) in clock arrival at SDRAM.
- JEDEC DIMM Clock delay spec is incorrect (.6ns is not possible!), and has no measurement method specified .
- Intel specifications define the clock structure, in good detail, but provide no measurement method or delay value (at DIMM-level).
3. System manufacturers have selected various clock delay measurement solutions and/or specs, driving suppliers to have inconsistent clock delays.
4. With increased SDRAM clock speeds (like PC133), as well as with DDR DIMMs emerging, improved clock definitions and measurement techniques are needed.
IBM designed, Major PC OEM approved
Memory module engineers from IBM have worked with engineers from Major Computer OEM to define a consistent measurement tool to ensure that PC133 and DDR product stardards are met. To tide down the standard and tolerance in their PC133 and DDR enablement effort. A two-pronged approach was taken:
- Define 'reference' nets for all new module standards. 'Reference' nets must permit both simulation and subsequent hardware validation.
- Define a 'Clock Reference Board', which can serve as a test vehicle for Module producers (to 'tune' the module assembly during validation and a a qualification vehicle for system producers.
Manufactured and Distributed by CST
As an active member of the JEDEC memory committee working with the memory industry for future solutions, CST is proud to be selected by IBM to manufacture and distribute this 'Clock Reference Board'.
- CST has a quality engineering and manufacturing in place.
- CST is a third party provider and does not compete with the memory module manufacturers.
- CST has good relationship and marketing channels to get to all the memory module producers.