It is a test board consisting of clock generator and buffer 4 of the buffered signal go to the DIMM socket while other clock signal go to a reference net. Clock delay and skew can be measured at the SDRAM chips on the module and then compared against the signal at the reference net.
It is for module design verification. It is the supplier’s quality standard to ensure consistent performance. It is an industry reference standard. It allows the tuning of PLL feed back on the module to balance the module timing. It is also an accepted JEDEC industry standard.
It is very easy to use. All you have to do is to connect an external power supply and 2 oscilloscope probes on it. You then turn it on and compare the signal time delay between the 2 signals. Depending on the skew of the clock signals, you will either tune the feedback of the PLL or change the clock loading to balance the skew.
Although this board was designed by IBM; Manufacturing, sales, distribution and after service support is solely responsible by CST, Inc. Call CST, Inc. at (972) 241-2662 for any concern on this product
This Clock Reference Board covers PC100 unbuffered modules, and PC133 registered modules. It has built-in regular clock or spread-spectrum mode. It is built with controlled impedance PC board for tightest performance tolerance. It has a separate Vcc plane that can be used for voltage shmooing test. It has extensive synthesizer de-coupling to assure stability. It also has marked test point for ease of use. All boards are built as one batch against a “golden board” to ensure consistency.