| Term |
Definition |
| SDRAM |
(Synchronous DRAM) A DRAM technology that uses a clock to synchronize signal input and output on a memory chip. The clock is coordinated with the CPU clock so the timing of the memory chips and the timing of the CPU are "in synch." The synchronization eliminates time delays and allows for fast consecutive read and write capability, thereby increasing the overall performance of the computer. SDRAM has two separate memory banks that operate simultaneously, while one bank prepares for access, the other is being accessed. SDRAM allows the CPU to access memory approximately 25 percent faster than EDO memory because it is controlled by the system clock. SDRAMs can only be used in computers designed for it and cannot be mixed with any other type of memory. SDRAM can operate at 100MHz, 133Mhz and features a burst mode that allows it to address blocks of information instead of small data bits. |
| Secondary Cache |
Cache that is second closest to the processor; typically located on the system board. Also referred to as Level 2 cache and external cache. |
| Self Refresh |
A memory technology that enables DRAM to refresh on its own-independent of the CPU or external refresh circuitry. This technology is built into the DRAM chip itself and reduces power consumption dramatically. It is commonly used in notebook and laptop computers. |
| SGRAM |
Synchronous Graphics RAM. A single port DRAM designed for graphics hardware that require high speed throughput such as 3-D rendering and full-motion video. |
| SIMM |
(Single In-line Memory Module) A memory package consisting of a number of DRAM chips on a small printed circuit board. This board provides the connection between multiple memory chips and the computer system. SIMMS come in various pin configurations, the most common type being: 30 pin and 72 pin. A 30 pin SIMM has a row of 30 tin or gold pins long the bottom of the module which determine the amount of data the module can handle. These pins connect to only one memory chip as opposed to DIMMs which can connect to multiple chips. |
| SIMM socket |
An interconnect component mounted on the system board, or motherboard, designed to hold a single SIMM |
| SO DIMM |
(Small Outline Dual In-line Memory Module) An enhanced version of a standard DIMM. The small outline DIMM is about half the length of a typical 72-pin SIMM. This compact DIMM are used in mobile computing devices. SO DIMMs come in a variety of pin
sizes and can be installed either singly to support 32-bit systems, or in pairs to support 64-bit systems. |
| Soft error |
An error caused by a temporary disruption of the memory cell |
| SOJ |
(Small Outline J-lead) A common form of surface-mount DRAM packaging. It is a rectangular package with J-shaped leads on the two long sides of the device. |
| SPDSerial Presence Detect |
(Serial Presence Detect) An enhanced presence detect that uses an EEPROM to store manufacturer data. |
| Speed |
The time it takes the RAM to put information into its memory or get
information out of its memory. It is measured from the time that an address
and proper control signals are given, until the information is stored or placed
in the device's output(s). |
| Speed grade |
Our coding for the speed that the stored information in the part can be
retrieved by a computer. For DRAMs, a -5 is 50 nanoseconds, a -6 is 60
nanoseconds, a -7 is 70 nanoseconds, etc. For SRAMs, a -10 is 10
nanoseconds, etc. |
| SRAM |
(Static RAM) SRAM is similar to DRAM but does not constantly refresh. SRAM is faster and more expensive than DRAM and is generally used for speed-critical areas of the computer such as cache memory. |
| Storage Device |
A medium designed to hold data, such as Floppy Diskette, Harrd Disk Drive or CD-ROM. |
| Synchronous Cache |
A kind of L2 cache that is synchronized with the CPU. This eliminates the lag time created while the CPU waits for cache memory to fulfill its requests. Synchronous cache is typically 3 to 5 percent faster than asynchronous cache, and is a full 20 percent faster than standard DRAM. See also Asynchronous Cache. |
