Understanding DDR4 Serial Presence Detect (SPD) Table

By: DocMemory

Introduction

Since I wrote “Understanding DDR Serial Presence Detect (SPD) Table” in 2003, I have been getting a lot a feedback from readers. I added “Understanding DDR2 Serial Presence Detect (SPD) Table” in 2006. Some of you told me that you are using these articles to train your employees and to introduce the mysteries SPD concept to your customers. I feel honored by your responses.

In 2007, I continued to add “Understanding DDR3 Serial Presence Detect (SPD) Table” to the series. Reader feedback was once again very positive.

Lately, CST has started shipment of a DDR4 EZ Programmer. Since the DD4 DIMM is introduced recently, I think this is the time to add an article for the DDR4 SPD Table. Due to the many more years of development, the DD4 SPD table has definitely gotten more sophisticated than the original DDR, DDR2 and DDR3 SPD table. Your attention is required to understand and follow through. I will try to use as much layman language as I can to accommodate you all.

Serial Presence Detect (SPD) data is probably the most misunderstood subject in the memory module industry. Most people only know it as the little Eeprom device on the DIMM that often kept the module from working properly in the computer. On the contrary, it is quite the opposite. The SPD data actually provide vital information to the system Bios to keep the system working in optimal condition with the memory DIMM. This article attempts to guide you through the construction of an SPD table with “Turbo-Tax” type of multiple choices questions. I hope you’ll find it interesting and useful.

Byte 0

Number of Serial PD Bytes Written/ SPD Device Size/ CRC Coverage

(When CST EZ-SPD Programmer is used: Simply select items from 3 tables and automatically calculate the final hex number)

The most common one used is:

Byte 1

SPD Revision

Byte 2

Byte 3

Byte 4

SDRAM Chip Size 

Byte 5

SDRAM Addressing

This byte describes the row addressing and column addressing in the SDRAM Device.

4Gb chips 

8Gb chips 

Byte 6

This byte describes the type of SDRAM Device on the module.

Byte 7

SDRAM Optional Features

Byte 8

Byte 9

Byte 10

Byte 11

Byte 12

Byte 13

Byte 14

Byte 15

Byte 16

Byte 17

Byte 18

Byte 19

Byte 20, CAS Latencies supported (First Byte)

Byte 21, CAS Latencies supported (Second Byte)

Byte 22, CAS Latencies supported (Third Byte)

Byte 23, CAS Latencies supported (Fourth Byte)

Thesse byte define which CAS Latency (CL) values are supported. The range is from CL=7 through CL=24with one bit per possible CAS Latency.

Byte 24

Byte 25

Minimum RAS to CAS delay Time (tRCDmin)

This word defines the minimum SDRAM RAS to CAS delay Time in medium timebase (MTB) units.

Based on fine timebase of 0.125ns

Byte 26

Byte 27

Byte 28

Byte 29

Byte 36

Byte 37

Byte 38

Byte 39

Byte 40

Byte 41-59

Byte 60 – 77

Connector to SDRAM Bit Mapping

More Examples:

Case 1: DQ0-3 is connected to First SDRAM in the sequence of 5,7,4,6 (that is DQ0 to SDRAM DQ5, DQ1 to SDRAM DQ7, DQ2 to SDRAM DQ4, and DQ3 to SDRAM DQ6), Bit 0-4 of SPD Byte 60 would be binary value of 01011. Since it is wired to the Upper Nibble of the SDRAM, we can add Bit 5 value (1) and Bit 6-7 (default 00) the binary value of Byte 60 become 00101011. Hex value of SPD Byte 60 would be 2Bh

Case 2: DQ4-7 is connected to First SDRAM in the sequence of 3,1,0,2 (that is DQ4 to SDRAM DQ3, DQ5 to SDRAM DQ1, DQ6 to SDRAM DQ0, and DQ7 to SDRAM DQ2), Bit 0-4 of SPD Byte 61 would be binary value of 10101. Since it is wired to the Lower Nibble of the SDRAM, we can add Bit 5 value (0) and Bit 6-7 (default 00) the binary value of Byte 61 become 00010101. Hex value of SPD Byte 61 would be 15h

Case 3: DQ8-11 is connected to Second SDRAM in the sequence of 1,3,2,0 (that is DQ8 to SDRAM DQ1, DQ9 to SDRAM DQ3, DQ10 to SDRAM DQ2, and DQ11 to SDRAM DQ0), Bit 0-4 of SPD Byte 62 would be binary value of 01100. Since it is wired to the Lower Nibble of the SDRAM, we can add Bit 5 value (0) and Bit 6-7 (default 00) the binary value of Byte 62 become 00001100. Hex value of SPD Byte 62 would be 0Ch

Case 4: DQ12-15 is connected to Second SDRAM in the sequence of 7,5,4,6 (that is DQ12 to SDRAM DQ7, DQ13 to SDRAM DQ5, DQ14 to SDRAM DQ4, and DQ15 to SDRAM DQ6), Bit 0-4 of SPD Byte 63 would be binary value of 10101. Since it is wired to the Upper Nibble of the SDRAM, we can add Bit 5 value (1) and Bit 6-7 (default 00) the binary value of Byte 63 become 00110101. Hex value of SPD Byte 63 would be 35h

Case 5: CB0-3 is connected to Fifth SDRAM in the sequence of 0,1,2,3 (that is CB0 to SDRAM DQ0, CB1 to SDRAM DQ1, CB2 to SDRAM DQ2, and CB3 to SDRAM DQ3), Bit 0-4 of SPD Byte 68 would be binary value of 00001. Since it is wired to the Lower Nibble of the SDRAM, we can add Bit 5 value (0) and Bit 6-7 (default 00) the binary value of Byte 68 become 00000001. Hex value of SPD Byte 68 would be 01h

Case 6: CB4-7 is connected to Fifth SDRAM in the sequence of 4,5,6,7 (that is CB4 to SDRAM DQ4, CB5 to SDRAM DQ5, CB6 to SDRAM DQ26, and CB7 to SDRAM DQ7), Bit 0-4 of SPD Byte 69 would be binary value of 00001. Since it is wired to the Upper Nibble of the SDRAM, we can add Bit 5 value (1) and Bit 6-7 (default 00) the binary value of Byte 69 become 00100001. Hex value of SPD Byte 69 would be 21h

Byte 78 – 116

Byte 117

Byte 118

Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group

Byte 119

Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group

Byte 120

Byte 121

Byte 122

Byte 123

Byte 124

Byte 125

Byte 126: Cyclical Redundancy code (CRC) for Base Configuration Section, LSB

Byte 127: Cyclical Redundancy code (CRC) for Base Configuration Section, MSB

Byte 128 – 255

Please refer to the annexes session after Byte 383.

Byte 320

Byte 321

Byte 322

Byte 323 - 324

Byte 325 - 328

Byte 329 - 348

(When CST EZ-SPD Programmer is used: Simply click the button at the right of Byte 128 to open an edit window, input the manufacturer’s PN (Maximum 18 digits). The software will automatically translate it into ASCII and write them into Bytes 329 - 348.)

Byte 349

Byte 350

Byte 351

Byte 352

DRAM Stepping

This byte defines the vendor die revision level (often call the “stepping”) of the DRAM s on the module. This byte is optional. For modules without DRAM stepping information, this byte should be programmed to 0xFF.

Byte 353 -381

Byte 382: cyclical Redundancy Code (CRC) for Manufacturer Section, LSB

Byte 383: cyclical Redundancy Code (CRC) for Manufacturer Section, MSB

This two-byte field contains the calculated CRC for bytes 320 – 381 in the SPD. Also see SPD bytes 126 -127 for a coding example.

Annexes for Byte 128 – Byte 255

Byte 128 (Unbuffered) : Raw Card Extension, Module Nominal Height

The Lower 5 bits of this byte define the nominal height (A dimension) in millimeters of the fully assembled module including heat spreaders or other added components. Refer to the relevant JEDEC JC-11 module outline (MO) documents for dimension definitions.

The upper 3 bits of this byte define revisions to the Raw Card beyond revision 3. If the revision level is within 3, it is defined on Byte 130, instead. Therefore, Bits 7-5 of Byte 128 is usually “000” unless the revision level is higher than 3.

Module Nominal Height

Byte 129 (Unbuffered): Module Maximum Thickness

Byte 130 (Unbuffered): Reference Raw Card Used

Byte 131 (Unbuffered): Address Mapping from Edge Connector to DRAM

The definition of standard and mirrored address connection mapping is detailed below; highlighted rows in table indicate which signals change between mappings.

Bytes 132 – 253 (Unbuffered):

Reserved must be coded 00h

Byte 254 (Unbuffered) : Cyclical Redundancy Code (CRC) for Module Specific Section, LSB

Byte 254 (Unbuffered) : Cyclical Redundancy Code (CRC) for Module Specific Section, LSB

This two-byte field contains the calculated CRC for bytes 128 – 253 in the SPD. See 126 – 127 for a coding example.

Annexes for Byte 128 – Byte 255

Annex K.2 Covers DDR4 RDIMM When Byte 2 = 0Ch Byte 3 = 01h

Byte 128 (Registered) : Raw Card Extension, Module Nominal Height

The Lower 5 bits of this byte define the nominal height (A dimension) in millimeters of the fully assembled module including heat spreaders or other added components. Refer to the relevant JEDEC JC-11 module outline (MO) documents for dimension definitions.

The upper 3 bits of this byte define revisions to the Raw Card beyond revision 3. If the revision level is within 3, it is defined on Byte 130, instead. Therefore, Bits 7-5 of Byte 128 is usually “000” unless the revision level is higher than 3.

Module Nominal Height

Byte 129 (Registered): Module Maximum Thickness

This byte defines the maximum thickness in millimeters of the fully assembled module including heat spreaders and any other components. It is in two parts; the front thickness (from PCB surface) and the back thickness (from PCB surface).

(When CST EZ-SPD Programmer is used: Simply selected by number between 1-15mm for front thickness and by number between 1-15mm for back thickness. Program automatically converts these thickness number into 2 byte hex code.)

Example:

Byte 130 (Registered): Reference Raw Card Used

This Byte indicates which JEDEC reference design raw card was used as the basis for the module assembly. It includes Raw Card designator and Revision number.

(When CST EZ-SPD Programmer is used: Simply select by number on revision code. Select Raw Card number by alphabetic code. Program automatically calculates the 2 byte Hex number.)

Byte 131 (Registered): DIMM Module Attributes

This byte indicates number of registers used on a module. Further it indicates number of rows of DRAM packages (monolithic, DDP or other stacked) parallel to edge connector (independent of DRAM orientation) on each side of the printed circuit board.

2. A Registered module with 2 rows of chips (either single, DDP, or stacked) and 2 registers is (0000 1010) = 0Ah

Byte 132 (Registered): RDIMM Thermal Heat Spreader Solution

Byte 133 (Registered): Register Manufacturer ID Code, Least Significant Byte

Byte 134 (Registered): Register Manufacturer ID Code, Most Significant Byte

This two-byte field indicates the manufacturer of the register used on the module, encoded as follows: the first byte is the number of continuation bytes indicated in JEP-106; the second byte is the last non-zero byte of the manufacturer’s ID code, again as indicated in JEP-106. These bytes are optional. For modules without the Register Manufacturer ID code information, both bytes should be programmed to 00h.

Examples:

Inphi Corporation Byte 133 = 04h Byte 134 = B3h

Montage Technology Byte 133 = 86h Byte 134 = 32h

Integrated Device Technology (IDT) Byte 133 = 80h Byte 134 = B3h

Byte 135 (Registered): Register Revision Number

This byte defines the vendor die revision level of the registering clock driver component. This byte is optional. For modules without the Register Revision Number information, this byte should be programmed FFh.

Byte 136 (Registered): Address Mapping from Register to DRAM

Byte 137 (Registered): Register Output Drive Strength for Control

Byte 138 (Registered): Register Output Drive Strength for CK

Bytes TBD – 253 (Registered):
These bytes are Reserved and must be coded as 00h

Byte 254 (Registered): Cyclical Redundancy Code (CRC) for Module specific Section, LSB.

Byte 254 (Registered): Cyclical Redundancy Code (CRC) for Module specific Section, MSB.

This two-byte field contains the calculated CRC for bytes 128 – 253 in the SPD. See bytes 126 -127 for a coding example.

Annexes for Byte 128 – Byte 255

Annex K.3 Covers DDR4 Load ReductionMemory Module (LRDIMM)

When Byte 2 = 0Ch Byte 3 = 04h

Byte 128 (Load Reduced) : Raw Card Extension, Module Nominal Height

The Lower 5 bits of this byte define the nominal height (A dimension) in millimeters of the fully assembled module including heat spreaders or other added components. Refer to the relevant JEDEC JC-11 module outline (MO) documents for dimension definitions.

The upper 3 bits of this byte define revisions to the Raw Card beyond revision 3. If the revision level is within 3, it is defined on Byte 130, instead. Therefore, Bits 7-5 of Byte 128 is usually “000” unless the revision level is higher than 3.

Module Nominal Height

Byte 129 (Load Reduced): Module Maximum Thickness

This byte defines the maximum thickness in millimeters of the fully assembled module including heat spreaders and any other components. It is in two parts; the front thickness (from PCB surface) and the back thickness (from PCB surface).

(When CST EZ-SPD Programmer is used: Simply selected by number between 1-15mm for front thickness and by number between 1-15mm for back thickness. Program automatically converts these thickness number into 2 byte hex code.)

Example:

Byte 130 (Load Reduced): Reference Raw Card Used

This Byte indicates which JEDEC reference design raw card was used as the basis for the module assembly. It includes Raw Card designator and Revision number.

(When CST EZ-SPD Programmer is used: Simply select by number on revision code. Select Raw Card number by alphabetic code. Program automatically calculates the 2 byte Hex number.)

Byte 131 (Load Reduced): DIMM Module Attributes

This byte indicates number of registers used on a module. Further it indicates number of rows of DRAM packages (monolithic, DDP or 3Dstacked) parallel to edge connector (independent of DRAM orientation) on each side of the printed circuit board.

For Example:

Byte 132 (Load Reduced): LRDIMM Thermal Heat Spreader Solution

Byte 133 (Load Reduced): Register and Data Buffer Manufacturer ID Code, Least Significant Byte

Byte 134 (Load Reduced): Register and Data Buffer Manufacturer ID Code, Most Significant Byte

This two-byte field indicates the manufacturer of the memory buffer used on the module, encoded as follows: the first byte is the number of continuation bytes indicated in JEP-106; the second byte is the last non-zero byte of the manufacturer’s ID code, again as indicated in JEP-106. These bytes are optional. For modules without the Register Manufacturer ID code information, both bytes should be programmed to 00h.

Byte 135 (Load Reduced): Register Revision Number

Byte 136 (Load Reduced): Address Mapping from Register to DRAM

This byte describes the connection of register output pins for address bits to the corresponding input pins of the DDR4 SDRAMs for rank 1 and rank 3 only; rank 0 and rank 2 are always assumed to use standard mapping. Only two connection types are supported, standard or mirrored, as described in the mapping table below.

The definition of standard and mirrored address connection mapping is detailed below; highlighted rows in table indicate which signals change between mappings.

Byte 137 (Load Reduced): Register Output Drive Strength for Control and Command/Address

This bye defines the drive strength for the registering clock driver outputs.

Byte 138 (Load Reduced): Register Output Drive Strength for CK

This byte defines the drive strength for the registering clock driver outputs.

Example:

All differential clocks are in Strong Drive mode 0000 10 10 = 0Ah

Byte 139 (Load Reduced): Data Buffer Revision Number

Byte 140 (Load Reduced): DRAM VrefDQ for Package Rank 0

This byte defines the VrefDQ value for the package rank 0 DRAMs.

On LRDIMM, the memory buffer re-drives the DQ lines to the particular rank of DRAM on the module. The DRAM reference voltage has to be trained to realize the optimum operation. This SPD byte tells the system the range of values to set the initial VrefDQ for training. Since the rising edge and the falling edge are asymmetrical, two ranges have to be considered. This setting is through MR6 A5 – A0 encoding.

VrefDQ Training Values

Byte 141 (Load Reduced): DRAM VrefDQ for Package Rank 1

Byte 142 (Load Reduced): DRAM VrefDQ for Package Rank 2

Byte 143 (Load Reduced): DRAM VrefDQ for Package Rank 3

Byte 144 (Load Reduced): Data Buffer VrefDQ for DRAM Interface

F5BCX: DRAM Interface VREF Control word definition

Byte 145 (Load Reduced): Data Buffer MDQ Drive Strength and RTT for data rate ≤1866

This Byte defines the drive strength for MDQ/MDQS outputs and the Read RTT termination strength of the data buffer component.

Example:

1. For MDQ Drive Strength = RZQ/5 (48Ω), MDQ Read Termination Strength = RZQ/6 (40Ω) at data rate ≤ 1866 Byte 145 = 0010 0011 = 23h

2. For MDQ Drive Strength = RZQ/6 (40Ω), MDQ Read Termination Strength = RZQ/4 (60Ω) at data rate ≤ 1866 Byte 145 = 0000 0001 = 01h

Byte 146 (Load Reduced): Data Buffer MDQ Drive Strength and RTT for 1866 < data rate ≤ 2400

This Byte defines the drive strength for MDQ/MDQS outputs and the Read RTT termination strength of the data buffer component.

Example:

1. For MDQ Drive Strength = RZQ/5 (48Ω), MDQ Read Termination Strength = RZQ/6 (40Ω) at 1866 < data rate ≤ 2400Byte 146 = 0010 0011 = 23h

2. For MDQ Drive Strength = RZQ/6 (40Ω), MDQ Read Termination Strength = RZQ/4 (60Ω) at 1866 < data rate ≤ 2400Byte 146 = 0000 0001 = 01h

Byte 147 (Load Reduced): Data Buffer MDQ Drive Strength and RTT for 2400 < data rate ≤ 3200

This Byte defines the drive strength for MDQ/MDQS outputs and the Read RTT termination strength of the data buffer component.

Example:

1. For MDQ Drive Strength = RZQ/5 (48Ω), MDQ Read Termination Strength = RZQ/6 (60Ω) at2400 < data rate ≤ 3200 Byte 147 = 0010 0001 = 21h

2. For MDQ Drive Strength = RZQ/6 (40Ω), MDQ Read Termination Strength = RZQ/4 (40Ω) at2400 < data rate ≤ 3200 Byte 147 = 0000 0011 = 03h

Byte 148 (Load Reduced): DRAM Drive Strength (for data rate ≤ 1866, 1866 < data rate ≤ 2400, and 2400 < data rate ≤ 3200)

This Byte defines the output buffer drive strength for the DRAMs.

Example:

1. 2400

2. 2400

Byte 149 (Load Reduced): DRAM ODT (RTT_WR and RTT_NOM) for data rate ≤ 1866

This Byte defines the ODT termination strength for the DRAMs.

Example:

1. For RTT_WR Drive Strength = 120Ω, RTT_NOM Strength = 60Ω at data rate ≤ 1866 Byte 149 = 0000 1001 = 09h

2. For RTT_WR Drive Strength = 80Ω, RTT_NOM Strength = 40Ω at data rate ≤ 1866 Byte 149 = 0010 0011 = 23h

Byte 150 (Load Reduced): DRAM ODT (RTT_WR and RTT_NOM) for 1866 < data rate ≤ 2400

This Byte defines the ODT termination strength for the DRAMs.

Example:

1. For RTT_WR Drive Strength = 120Ω, RTT_NOM Strength = 60Ω at 1866 < data rate ≤ 2400 Byte 150 = 0000 1001 = 09h

2. For RTT_WR Drive Strength = 80Ω, RTT_NOM Strength = 40Ω at 1866 < data rate ≤ 2400 Byte 150 = 0010 0011 = 23h

Byte 151 (Load Reduced): DRAM ODT (RTT_WR and RTT_NOM) for 2400 < data rate ≤ 3200

This Byte defines the ODT termination strength for the DRAMs.

Example:

1. For RTT_WR Drive Strength = 120Ω, RTT_NOM Strength = 60Ω at 2400 < data rate ≤ 3200 Byte 151 = 0000 1001 = 09h

2. For RTT_WR Drive Strength = 80Ω, RTT_NOM Strength = 40Ω at 2400 < data rate ≤ 3200 Byte 151 = 0010 0011 = 23h

Byte 152 (Load Reduced): DRAM ODT (RTT_PARK) for data rate ≤ 1866

This Byte defines the ODT termination strength for the DRAMs

.

Example:

1. For RTT_PARK Drive Strength = 60Ω, at data rate ≤ 1866 Byte 152 = 0000 0001 = 01h

2. For RTT_PARK Drive Strength = 120Ω, at data rate ≤ 1866 Byte 152 = 0000 0010 = 02h

Byte 153 (Load Reduced): DRAM ODT (RTT_PARK) for 1866 < data rate ≤ 2400

This Byte defines the ODT termination strength for the DRAMs.

Example:

1. For RTT_PARK Drive Strength = 60Ω, at 1866 < data rate ≤ 2400 Byte 153 = 0000 0001 = 01h

2. For RTT_PARK Drive Strength = 120Ω, at 1866 < data rate ≤ 2400 Byte 153 = 0000 0010 = 02h

Byte 154 (Load Reduced): DRAM ODT (RTT_PARK) for 2400 < data rate ≤ 3200

This Byte defines the ODT termination strength for the DRAMs.

Example:

1. For RTT_PARK Drive Strength = 60Ω, at 2400 < data rate ≤ 3200 Byte 154 = 0000 0001 = 01h

2. For RTT_PARK Drive Strength = 120Ω, at 2400 < data rate ≤ 3200 Byte 154 = 0000 0010 = 02h

Bytes 155 – 253 (Load Reduced):

Reserved – must be coded 00h

Byte 254 (Load Reduced): Cyclical Redundancy Code (CRC) for Module specific Section, LSB.

Byte 254 (Load Reduced): Cyclical Redundancy Code (CRC) for Module specific Section, MSB.

This two-byte field contains the calculated CRC for bytes 128 – 253 in the SPD. See bytes 126 -127 for a coding example.

Final Note:

Everything in the above article and more are now implemented into the CST EZ-SPD DDR4 Programmer software. The features are:

.....just to name a few.

For further information, please view : www.simmtester.com

By: DocMemory
Copyright © 2013 CST, Inc. All Rights Reserved