| Term |
Definition |
| Access Time, timing |
A measurement of time in nanoseconds (ns) used to indicate the speed of memory. Access time is a cycle that begins the moment the CPU sends a request to memory and ends the moment the CPU receives the data it requested. Memory modules complete this process in as fast as 6ns for PC133mhz memory while older modules can take up to 80ns or more. |
| Array |
The area of the RAM that stores the bits. The array consists of rows and columns, with a cell at each intersection that can store a bit. The large rectangular section in the centre of the die where the memory is stored. |
| ASCII |
(American Standard Code for Information Interchange) A method of encoding text as binary values. The ASCII system requires nearly 256 combinations of 8-bit binary numbers to support every possible keystroke from the keyboard. |
| Asynchronous Cache |
Describes a type of L2 cache that is not in synch with the system clock. Asynchronous cache is slower than its synchronous counterpart, but is capable of delivering information to the CPU at a rate 10 percent faster than standard DRAM. Asynchronous cache was first used to boost memory performance in 386 systems and is still widely used today. |
| Bandwidth |
The capacity to move data on an electronic line such as a bus or a channel. In short, the amount of data moved relative to a specific time frame. It is expressed in bits, bytes, or Hertz (cycles) per second. |
| Bank Schema |
A method of diagramming memory configurations. The bank schema system consists of rows and columns that represent memory sockets on a system: rows indicate independent sockets and columns represent banks of sockets. |
| BEDO |
(Burst EDO) DRAM -- a type of EDO DRAM that can process four memory addresses in one burst. Unlike SDRAM, however, BEDO DRAM can only stay synchronised with the CPU clock for short periods (bursts) and it can't keep up with processors whose buses run faster than 66 MHz. |
| Binary |
A method of encoding numbers as a series of bits. The binary number system, also referred to as base 2, uses combinations of only two digits - 1 and 0. |
| Bit |
Short for binary digit, the smallest unit of data that can be processed or stored by a computer. A bit can have a value of either 1 or 0. Bits make up 'computer' language the same way letters of an alphabet make up human languages. Different combinations of different bits form 'words' and 'sentences' (actually signals) that a computer understands. Before these words and sentences can be transmitted from the CPU to memory, or vice versa, they must be broken down into 8-bit segments called bytes. Older computers were designed to handle only 8-bit data segments, while newer models have progressed to 64-bit segments. This larger bit width capacity generally means better and faster computer performance. |
| Buffered |
Buffered means adding logic, particularly drivers, to a SIMM or DIMM to increase the output current. Buffering is used to overcome signal attenuation due to capacitive loading. Modules that are "buffered" usually have small buffer chips mounted on them. |
| Burst Mode |
Bursting is a rapid data-transfer technique that automatically generates a block of data (a series of consecutive addresses) every time the processor requests a single address. The assumption is that the next data-address the processor will request will be sequential to the previous one. Bursting can be applied both to read operations (from memory) and write operations (to memory). |
| Bus |
The central communication avenue in a PCs system board. It normally consists of a set of parallel wires or signal traces that connect the CPU, the memory, all input/output devices, and peripherals and allows data to be transferred from one system component to another. Busses come in a variety of bit widths and speeds. To prevent data bottlenecks, the components attached to a bus
must operate at close to the same speed as the bus. |
| Bus cycle |
A single transaction between system memory and the CPU. |
| Byte |
A unit of information made up of 8 bits. The byte is the fundamental unit of computer processing; almost all aspects of a computer's performance and specifications are measured in bytes or multiples of bytes such as kilobytes (~1,000 bytes) or megabytes (~1 million bytes), or gigabytes (~ 1 billion bytes) |
| Cache Controller |
The circuit in control of the interface between the CPU, cache and DRAM (main memory). |
| Cache memory |
Cache RAM is high-speed memory (usually SRAM) which is dedicated to storing frequently requested data. If the CPU needs data, it will check in the high-speed cache memory first before looking in the slower main memory. Cache memory may be three to five times faster than system DRAM. Most computers have two separate memory caches; L1 cache, located on the CPU, and L2 cache, located between the CPU and DRAM. L1 cache is faster than L2, and is the first place the CPU looks for its data. If data is not found in L1 cache, the search continues with L2 cache, and then on to DRAM. |
| Card Memory |
A type of memory typically used in laptop and notebook computers. Credit card memory features a small for factor and is named for its similarity to the size of credit card. |
| CAS |
(Column Address Select/or Strobe)--A control pin on a DRAM used to and activate a column address. The column selected on a DRAM is determined by the data present at the address pins when CAS becomes active |
| CAS Latency |
The ratio between column access time and clock cycle time. CAS Latency 2 (CL2) offers a slight performance increase over CAS Latency 3 (CL3).
|
| CBR |
(CAS Before RAS)- a fast refresh technique in which the DRAM keeps track of the next row it needs to refresh, thus simplifying what a system would have to do to refresh the part. |
| Check Bits |
Extra data bits provided by a DRAM module to support ECC function. For a 4-byte bus, 7 or 8 check bits are needed to implement ECC, resulting in a total bus width of 39 or 40 bits. On an 8-byte bus, 8 additional bits are required, resulting in a bus width of 72 bits. |
| Checkboard |
A detail test pattern designed to exercise each individual cell in the memory and find possible shorts between adjacent columns and data buses |
| Clock |
An electrical current that alternates between high and low voltages. The speed of the clock is measured in Megahertz (MHz) |
| Clock speed |
The rate at which a computer's internal system clock operates. The clock is used to synchronize operations between the components within the clock. |
| CMOS |
Complementary Metal Oxide Semiconductor: a process that uses both N- and P-channel devices in a complimentary fashion to achieve small geometries and low power consumption. |
| Column |
Part of the memory array. A bit can be stored where a column and a row intersect. |
| Compact Flash Memory |
A fast, postage stamp size RAM that is removable. The CF Card weighs half an ounce, with roughly one-fourth the volume and one-half the thickness of a PCMCIA Type II Card. The CF Card fits into a CF PC Card Adapter making it compatible with a standard PCMCIA Type II slot on any notebook or desktop computer. This allows the easy transfer of stored digital information from the CF Card to a computer or printer. Currently, the most readily available application for the CompactFlash Card is the digital still camera. |
| CPU |
(Central Processing Unit)--The chip in a computer that has primary responsibility for interpreting commands and running programs. The CPU is the most vital component of a computer system. The speed of the CPU has a significant impact on overall system performance, but the CPU doesn't act alone. If slower memory is paired with a fast processor, the processor will be forced to wait for the memory to respond. When the speed mismatch is extreme, the user will see numerous memory errors and even complete system failure. |
| DDR |
(Double Data Rate) or DDR SDRAM The next generation of the current SDRAM. DDR finds its foundations on the same design core of SDRAM, yet adds advances to enhance its speed capabilities. As a result, DDR allows data to be read on both the rising and the falling edge of the clock, delivering twice the bandwidth of standard SDRAMS. DDR essentially doubles the memory speed from SDRAMs without increasing the clock frequency |
| DIMM |
(Dual In-line Memory Module) A printed circuit board with gold or tin/lead contacts and memory devices. A DIMM is similar to a SIMM, but with this primary difference: unlike the leads on either side of a SIMM, which are "tied together" electrically, the leads on either side of a DIMM are electrically independent, ie actually separate circuits which allows for wider and faster data transfer. |
| DIP |
(Dual In-line Package) A form of DRAM component packaging. DIPs can be installed either in sockets or permanently soldered into holes extending into the surface of the printed circuit board. The DIP package was extremely popular when it was common for memory to be installed directly on a computer's motherboard. |
| DQM |
Data mask signal used by SDRAMs to provide byte masking during write operations. There is one DQM signal for every 8 bits of data width. |
| DRAM |
(Dynamic Random Access Memory) DRAM is the most common type of memory and is "dynamic" because in order for the memory chip to retain data, it must be refreshed constantly (every few milliseconds). If the cell is not refreshed, the data is lost. DRAM temporarily stores data in a cell composed of a capacitor and a transistor. Each cell contains a specified number of bits. These cells are accessed by row addresses and column addresses. |
| DRDRAM |
(Direct Rambus DRAM)-- a totally new RAM architecture, complete with bus mastering (the Rambus Channel Master) and a new pathway (the Rambus Channel) between memory devices (the Rambus Channel Slaves). A single Rambus Channel has the potential to reach 500MBps in burst mode; a 20-fold increase over DRAM. |
| ECC |
(Error Checking/ Correcting Code) A method used to check the integrity of data stored in memory . ECC memory improves data integrity by detecting errors in memory and is more advanced than parity because it can detect both multiple-bit errors and single-bit errors (parity only detects single-bit errors). ECC is typically found in high-end PCs and file servers where data integrity is key.
An ECC scheme capability is partially determined by the sophistication of the "systematic code" employed. The systematic code is like a reference table that the memory system uses to determine whether or not the memory has returned the correct data. Every time data is stored in memory, this code is responsible for the generation of check bits which are stored along with the data. When the contents of a memory location is referenced, the ECC memory logic uses the check bit information and the data itself to generate a series of "syndrome bits". If these syndrome bits are all zeros, then the data is valid and operation continues. If any bits are ones, then the data has an error and the ECC memory logic isolates the errors and reports them in the operating system. In the case of a correctable error, the ECC memory scheme can detect single and double bit errors and correct single bit errors. |
| EDO Parity RAM |
EDO Parity RAM offers the high performance of EDO memory and has built-in parity which greatly improves reliability. Ideal for high-end PCs and entry-level servers, EDO Parity modules are compatible with any system that accepts a standard 72-pin EDO module and are rapidly becoming the new standard on high-end systems. |
| EDO RAM |
(Extended Data Out) EDO RAM is similar to FPM memory, a form of DRAM technology that shortens the read cycle between memory and CPU. but provides improved performance by keeping available data longer in memory. It eliminates much of the wait time by allowing the processor to access data during the refresh cycle. In other words, the computer can load data as it is searching for new information. EDO memory is generally 10 to 20% faster than FPM memory. A computer must support EDO memory in order to notice an increase in performance. |
| EDRAM |
(Enhanced Dynamic Random Access Memory)--a form of DRAM that boosts performance by placing a small complement of static RAM (SRAM) in each DRAM chip and using the SRAM as a cache. Also known as cached DRAM, or CDRAM.
|
| EEPROM |
Electrically Erasable, PROgrammable, Read-Only Memory chip. EEPROMs differ from DRAMs in that the memory stays in even if electrical power is lost. Also, the memory can be erased and reprogrammed. |
| EOS |
(ECC on SIMM) A data-integrity checking technology designed by IBM that features ECC data-integrity checking built onto a SIMM. |
| EPROM |
Erasable Programmable Read Only Memory |
| Even Parity |
Even parity and odd parity are two different parity protocols used to check the integrity of data stored in memory. A memory manufacturer can use either protocol in a memory product. Even parity adds an additional bit to every byte of data to make the total number of 1's in the segment even. When the byte passes to the CPU, the parity circuit checks the byte to be sure it is still even. If it is, the data is considered to be valid and the parity bit is removed from the byte. If instead it registers as odd, it is considered to be invalid and a parity error is generated. |
| Fake Parity |
Unlike odd and even parity, fake parity is not capable of detecting an invalid data bit. It was designed to artificially 'satisfy' a parity-enabled computer without actually checking the data for errors. Fake parity attaches a bit to each byte of data just like odd and even parity protocols. The difference is that fake parity simply adds the correct parity bit as the data is sent to the CPU instead of attaching it before the data is stored to memory, and recalculating it before the byte passes to the CPU. |
| Flash Memory |
Flash memory is a non-volatile memory device that retains its data when the power is removed. The device is similar to EPROM with the exception that it can be electrically erased, whereas an EPROM must be exposed to ultra-violet light to erase.Flash memory does not need a constant power supply to retain its data and it offers extremely fast access times, low power consumption, and relative immunity to severe shock or vibration. These qualities combined with its compact size, make it perfect for portable devices like scanners digital cameras, cell phones, pagers, handhelds and printers. Flash chips have a lifespan limited to 100,000 write cycles, which means flash will never replace main memory in
computers. |
| FPM |
(Fast-Page Mode) A common DRAM data-access scheme. Accessing DRAM is similar to finding information in a book. First, you turn to a particular page, then you select information from the page. Fast-page mode enables the CPU to access new data in half the normal access time, as long as it is on the same page as the previous request. |
| Gigabit |
Approximately 1 billion bits: 1 bit x 1,024 (that is, 1,073,741,824 bits) Or exactly 2^30 bits. |
| Gigabyte, GB |
A unit of measurement approximately equal to 1024 megabytes. Computer components process data in bytes or multiples of bytes such as kilobytes (~1,000 bytes), megabytes (~1 million bytes), and gigabytes (~ 1 billion bytes). |
| Integrated Circuit, IC |
An electronic circuit-consisting of components and connectors-contained on a semiconductor chip. Usually packaged in a plastic or ceramic case with external connector pins. |
| IO CARD |
A PCB that interfaces between the computer and our own interface board. |
| JEDEC |
(Joint Electronic Devices Engineering Council) An international body of Semiconductor manufacturers that set integrated circuit standards. |
| Keys |
Notches on a memory module that prevent it from being installed incorrectly
or into an incompatible system. |
| Kilobit |
Approximately one thousand bits: 1 bit x 210 (that is, 1,024 bits). |
| Kilobyte, KB |
A unit of measurement approximately equal to 1024 bytes. Computer components process data in bytes or multiples of bytes such as kilobytes (~1,000 bytes), megabytes (~1 million bytes), and gigabytes (~ 1 billion bytes).
|
| L1 cache |
(L1 Cache)- Sometimes also known as primary or level 1 cache, is a small amount of high-speed memory that resides on or very close to the CPU. L1 Cache interacts with the CPU for most frequently requested instructions and data.
|
| L2 cache |
(L2 cache) A specialized memory unit that enhances DRAM performance by providing the CPU with data at speeds ten times faster than DRAM. L2 cache comprised of Static RAM (SRAM), a high-speed RAM that does not need to be refreshed to retain its data. Most computers have two different memory caches; L1 cache, located on the CPU, and L2 cache, located between the CPU and DRAM. L1 cache is faster than L2, and is the first place the CPU looks for its data. If data is not found in L1 cache, the search continues |
| Logic Board |
(see motherboard) |
| Marching |
Detail test pattern designed to check for decoder and cell interaction problems |
| Megabit |
Approximately one million bits: 1 bit x 1,0242 (that is, 1,048,576 bits). |
| Megabyte, MB |
(MB) A unit of measurement approximately equal to 1 million bytes (1,048,576 to be exact). |
| Memory |
A Term commonly used to refer to computer system's random access memory (see also RAM). The term memory has also been used to refer to all types of electronic data storage (see storage). A computer system's memory is crucial to its operation; without memory, a computer could not read programs or retain data. Memory stores data electronically in memory cells contained in chips. The two most common types of memory chips are DRAM and SRAM |
| Memory Bank |
A logical unit of memory in a computer, the size of which is determined by the computer's CPU. For example, a 32-bit CPU calls for memory banks that provide 32 bits of information at a time. |
| Memory Configuration |
The amount of memory in an IC and how it is accessed. Also, a code on the lot traveler used to indicate the IC's memory configuration (e.g., 1M1 = 1 Meg x 1, 4M4 = 4 Meg x 4, etc.). |
| Memory Controller |
The interface between system memory and the central processing unit. The memory controller consists of special circuitry--usually a microprocessor--within a computer system that interprets requests from the central processing unit in order to locate data locations, or addresses, in memory. |
| Memory Cycle |
Minimum amount of time required for a memory to complete a cycle such as read, write, read/write, or read/modify/write. |
| MIPS |
(MIPS) Millions of Instructions Per Second. This measurement is generally used when describing the speed of computer systems |
| Motherboard |
Also known as logic board, main board, or system board; your computer's main electronics board, which in most cases either contains all CPU, memory, and I/0 functions, or has expansion slots that support them. |
| Nanosecond, ns |
One billionth of a second. Memory data access times are measured in nanoseconds. For example, memory access times for typical 30- and 72-pin SIMM modules range from 60 to 100 nanoseconds. |
| Non-Volatile Memory |
Types of memory that retain their contents when power is turned off. ROMs, PROMs, EPROMs and flash memory are examples. Sometimes the term refers to memory that is inherently volatile, but maintains its content because it is connected to a battery at all times, such as CMOS memory and to storage systems, such as hard disks. |
| Noncomposite |
A term created by Apple Computer, Inc. that describes a memory module which uses 16-Mbit technology. For a given capacity, a noncomposite module will have fewer chips than a composite module. |
| Odd Parity |
Even parity and odd parity are two different parity protocols used to check the integrity of data stored in memory. A memory manufacturer can use either protocol in a memory product. Odd parity adds an additional bit to every byte of data to make the total number of 1s odd. When the byte passes to the CPU, the parity circuit checks the byte to be sure it is still odd. If it is, the data is considered to be valid and the parity bit is stripped from the byte. If instead it registers as even, it is considered to be invalid and a parity error is generated. |
| Parity |
A quality control method that checks the integrity of data stored in a computer's memory. Parity works by adding an extra bit of data to each byte to make the total number of 1's either odd or even An error is detected if the parity circuit determines that this number has changed, indicating that some of the data may have been lost or otherwise corrupted. Two different parity protocols exist, even parity and odd parity. Parity protocols are capable of detecting single bit errors only. To enable multiple-bit error detection, manufacturers must use a more advanced form of error checking called Error Correcting Code (ECC). See also Fake Parity |
| PC133 PC100 PC66 |
Around middle of 1998, Intel introduced the BX chip set to their motherboard designs. One element in this new architecture will include an increase in the PC main memory bus speed (Host bus) from 66 to 100 to 133 MHz, called PC 133. To match the 133MHz bus speed, 133MHz SDRAM modules is the required memory technology for this new chip set. |
| PCB |
(Printed Circuit Board) A component made up of layers of copper and fiberglass; the surface of a PCB features a pattern of copper lines, or "traces," that provide electrical connections for chips and other components that mount on the surface of the PCB. Examples: motherboard, SIMM, credit card memory, and so on. |
| PCMCIA |
(Personal Computer Memory Card International Association) A standard that allows interchangeability of various computing components on the same connector. The PCMCIA standard is designed to support input/ output devices, including memory, fax/modem, SCSI, and networking products. |
| Pipeline Burst Cache |
A type of synchronous cache that uses two techniques to minimise processor wait states - a burst mode that pre-fetches memory contents before they are requested, and pipelining so that one memory value can be accessed in the cache at the same time that another memory value is accessed in DRAM. |
| Primary Cache |
Cache that is closest to the processor: typically located inside the CPU chip. Can be implemented either as a unified cache or as separate sections for instructions and data. Also referred to as Level 1 cache or internal cache. |
| Proprietary Memory |
Memory that is custom-designed for a specific computer |
| RAM |
(Random Access Memory) A type of memory that can be written to and read from in a nonlinear (random) manner. When an application is opened. it is transferred from the hard drive to RAM where it is more readily accessible. RAM enhances system performance because it can process requests from the CPU more quickly than the hard drive. The kind of RAM used in main memory on most computers is Dynamic RAM (DRAM). DRAM stores data as electronic signals. These signals must be constantly refreshed to
keep them from dissipating. The more RAM your computer has, the more data it can store at one time and subsequently the more efficiently your computer will operate. The data held in RAM is lost when the computer is turned off. The term random derives from the fact that the CPU can retrieve data from any individual location, or address, within RAM. |
| RAS |
Row Address Select (or Strobe): a control pin on a DRAM used to latch and activate a row address. The row selected on a DRAM is determined by the data present at the address pins when RAS becomes active. |
| RDRAM |
Rambus DRAM technology is a system-wide, chip-to-chip interface design that allows data to pass through a simplified bus. Rambus uses a unique RSL (Rambus Signaling Logic) technology. Rambus is available in two flavors: RDRAM and Concurrent RDRAM. RDRAM is currently in production with Concurrent RDRAM production scheduled for late 1997. The third line extension, Direct RDRAM, is in development stages and scheduled for production in 1999. In late 1996, Rambus agreed to a development and license contract with Intel that will lead to Intel's PC chip sets supporting Rambus memory starting in 1999. |
| Refresh |
An electrical process used to maintain data stored in DRAM. The process of refreshing electrical cells on a DRAM component is similar to that of recharging batteries. Different DRAM components call for different refresh methods. |
| Refresh Rate |
The speed at which DRAM is refreshed. DRAM stores data as a series of electron charges in individual cells. This data must be constantly recharged or 'refreshed' to keep the data from dissipating. The refresh rate refers to the size of the data that must be recharged, and is typically expressed in kilobytes (~1,000 bytes). Two common refresh rates are 2K and 4K, with 2K being the faster rate. |
| Registered Memory |
Registers delay memory information for one clock cycle to ensure all communication from the chipset is collected by the clock edge, providing a controlled delay on heavily loaded memories |
| RIMM |
(Rambus Inline Memory Module)--A form of chip packaging that is similar to DIMMs using Direct Rambus DRAM memory subsystems. |
| ROM |
(Read Only Memory) A form of random access memory that can only be read from, not written to. Most systems use ROM to store the instructions a computer needs during the startup process. |
| Row |
Part of the RAM array; a bit can be stored where a column and a row intersect. |
| SDRAM |
(Synchronous DRAM) A DRAM technology that uses a clock to synchronize signal input and output on a memory chip. The clock is coordinated with the CPU clock so the timing of the memory chips and the timing of the CPU are "in synch." The synchronization eliminates time delays and allows for fast consecutive read and write capability, thereby increasing the overall performance of the computer. SDRAM has two separate memory banks that operate simultaneously, while one bank prepares for access, the other is being accessed. SDRAM allows the CPU to access memory approximately 25 percent faster than EDO memory because it is controlled by the system clock. SDRAMs can only be used in computers designed for it and cannot be mixed with any other type of memory. SDRAM can operate at 100MHz, 133Mhz and features a burst mode that allows it to address blocks of information instead of small data bits. |
| Secondary Cache |
Cache that is second closest to the processor; typically located on the system board. Also referred to as Level 2 cache and external cache. |
| Self Refresh |
A memory technology that enables DRAM to refresh on its own-independent of the CPU or external refresh circuitry. This technology is built into the DRAM chip itself and reduces power consumption dramatically. It is commonly used in notebook and laptop computers. |
| SGRAM |
Synchronous Graphics RAM. A single port DRAM designed for graphics hardware that require high speed throughput such as 3-D rendering and full-motion video. |
| SIMM |
(Single In-line Memory Module) A memory package consisting of a number of DRAM chips on a small printed circuit board. This board provides the connection between multiple memory chips and the computer system. SIMMS come in various pin configurations, the most common type being: 30 pin and 72 pin. A 30 pin SIMM has a row of 30 tin or gold pins long the bottom of the module which determine the amount of data the module can handle. These pins connect to only one memory chip as opposed to DIMMs which can connect to multiple chips. |
| SIMM socket |
An interconnect component mounted on the system board, or motherboard, designed to hold a single SIMM |
| SO DIMM |
(Small Outline Dual In-line Memory Module) An enhanced version of a standard DIMM. The small outline DIMM is about half the length of a typical 72-pin SIMM. This compact DIMM are used in mobile computing devices. SO DIMMs come in a variety of pin
sizes and can be installed either singly to support 32-bit systems, or in pairs to support 64-bit systems. |
| Soft error |
An error caused by a temporary disruption of the memory cell |
| SOJ |
(Small Outline J-lead) A common form of surface-mount DRAM packaging. It is a rectangular package with J-shaped leads on the two long sides of the device. |
| SPDSerial Presence Detect |
(Serial Presence Detect) An enhanced presence detect that uses an EEPROM to store manufacturer data. |
| Speed |
The time it takes the RAM to put information into its memory or get
information out of its memory. It is measured from the time that an address
and proper control signals are given, until the information is stored or placed
in the device's output(s). |
| Speed grade |
Our coding for the speed that the stored information in the part can be
retrieved by a computer. For DRAMs, a -5 is 50 nanoseconds, a -6 is 60
nanoseconds, a -7 is 70 nanoseconds, etc. For SRAMs, a -10 is 10
nanoseconds, etc. |
| SRAM |
(Static RAM) SRAM is similar to DRAM but does not constantly refresh. SRAM is faster and more expensive than DRAM and is generally used for speed-critical areas of the computer such as cache memory. |
| Storage Device |
A medium designed to hold data, such as Floppy Diskette, Harrd Disk Drive or CD-ROM. |
| Synchronous Cache |
A kind of L2 cache that is synchronized with the CPU. This eliminates the lag time created while the CPU waits for cache memory to fulfill its requests. Synchronous cache is typically 3 to 5 percent faster than asynchronous cache, and is a full 20 percent faster than standard DRAM. See also Asynchronous Cache. |
| Tag |
The subset of the CPU address bits used to compare the tag bits of the cache directory to the main memory address being accessed. |
| Tag RAM |
Cache is physically divided into two sections. The Tag RAM section stores the Tag address of the location of the data in cache. This section is smaller than the Data RAM section, which stores the actual data or instruction. |
| TSOP |
(Thin Small Outline Package) A type of DRAM package that uses gullwing shaped leads on both sides. TSOP DRAM mounts directly on the surface of the printed circuit board. The advantage of the TSOP package is that it is one-third the thickness of an SOJ package. TSOP components are commonly used in small outline DIMM and credit card memory applications. |
| Type |
This number (x8, x9, x32, x36, x64, x72, x80) refers to the bit depth of a module, or to the size of the data path used to access the memory. |
| Unbuffered Memory |
This is where the chipset controller deals directly with the memory. There is nothing between the chipset and the memory as they communicate with each other. |
| Vcc |
Collector Common Voltage. |
| Volatile Memory |
Memory that loses its contents when the power is turned off. A computer's main memory, made up of dynamic RAM or static RAM chips, loses its content immediately upon loss of power. Contrast ROM, which is non-volatile memory. |
| VRAM |
(Video RAM) VRAM has two separate data ports. One is dedicated to updating the image on the screen while the other one is used for changing the image data stored in memory. This "dual-ported" design gives higher performance than DRAM which cannot read and write simultaneously but is more expensive. |
