The disclosure could be a bad sign for the EUV community, which has been hoping to insert the next-generation lithography technology at the 32-nm node in the 2009 time frame. It also raises more questions about the readiness — or viability — of EUV, which has been hampered by lack of suitable power sources, photoresists and other critical pieces of the puzzle. Plus, if or when an EUV tool gets shipped, the price tag could run from $40-to-$60 million per copy.

The industry hopes EUV will make it into production sooner than latter, but the technology must reach certain milestones. ''I think the next 9 to 12 months are very critical to achieve this,'' said George Gomba, IBM distinguished engineer and director of lithography technology development at the company.

Like most leading-edge chip makers, IBM has been exploring EUV, immersion, direct-write and other technologies in the next-generation lithography (NGL) front. Within its leading-edge, 300-mm production fab in East Fishkill, N.Y., the company has been using 193-nm optical scanners from ASML Holding NV. It is widely believed that IBM will continue to work with the Dutch company going forward. IBM did not comment on its vendors.

At IBM, the company is using ''dry'' 193-nm immersion lithography tools for the production of logic chips at the 65-nm node. Then, in its current roadmap, IBM will use 193-nm immersion lithography for logic production at the 45-nm node (65-nm half-pitch), Gomba said. At the node, IBM will use a 193-nm immersion scanner with a numerical aperture of 1.2, which is reportedly supplied by ASML.

IBM is expected to move into 45-nm production by ''year-end 2007,'' he said. ''Basically, immersion is ready for prime time in production in 2007,'' he declared in a phone interview.

Following the 45-nm node, IBM will extend 193-nm immersion down to the 32-nm node (45-nm half-pitch) for logic, he said. At the node, the company is exploring both single- and double-patterning techniques, with a scanner equipped with a 1.35 NA lens.

Surprisingly, the company claims it will push immersion down to the 22-nm node for logic, which is due in the 2011 time frame. ''I believe [193-nm immersion] will be the only solution that meets the two-year cycle and requirements at 22-nm,'' he said.

The current limit for 193-nm immersion, with a refractive index of 1.44, is around the production of devices at 40-nm, according to experts. To go beyond this barrier, IBM is expected to use resolution enhancement techniques and OPC, in addition to an advanced 193-nm immersion scanner with double-patterning technology. ''We are exploring different types of double-patterning techniques,'' Gomba said.

What about EUV? IBM believes that EUV ''will not be ready for the early development work'' at 22-nm, Gomba said. IBM hopes that EUV would be ready to ''intersect'' the production phases of the 22-nm node for logic, but the technology must reach certain milestones by the 2009 time frame.

So far, ASML has shipped two rather early ''demo'' EUV tools, including one to IMEC and another to Albany Nanotech. The Dutch company is expected to ship a ''pre-production'' model to Samsung and possibly Intel Corp. Nikon Corp. and Canon Inc. are also working on EUV.

The IBM lithography guru, meanwhile, is also pessimistic about nano-imprint and maskless lithography (ML2) for production at these advanced nodes. ''We don't think it will be ready,'' he said.

Other chip makers are also expected to emulate IBM's lithography roadmap. In fact, IBM is working with several partners on the lithography front. In 2005, IBM, Advanced Micro Devices Inc., Infineon Technologies AG, and Micron Technology Inc. joined forces with ASML and KLA-Tencor Corp. in a $600 million seven-year lithography consortium, dubbed INVENT.

Another partner, silicon foundry provider Chartered Semiconductor Manufacturing Pte. Ltd., is also expected to emulate IBM's strategy. Other foundries, including UMC and TSMC, are expected to insert immersion at the 45-nm node or sooner.

Intel is the exception to the rule. Last year, Intel revealed that it would not use immersion lithography to characterize its chips at the 45-nm node. Instead, Intel (Santa Clara, Calif.) plans to extend its existing and conventional 193-nm wavelength ''dry'' scanners for use in processing the critical layers at the 45-nm node.

Intel may deploy immersion at its 32-nm node. The chip giant has also been a major proponent of EUV, with plans to insert the technology at 32-nm or beyond.

By: DocMemory
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