Tuesday, March 6, 2007
TSMC unveils the first embedded DRAM based on 65-nanometer process for Nvidia Corp. to be used in its latest mobile GPU, the foundry said.
TSMC's 65nm embedded DRAM process and IP shrinks the cell and macro size by nearly 50 percent compared to its previous generation. The foundry is targeting the higher bandwidth offered by the embedded DRAM at applications such as game consoles, high-end networking, digital consumer, and multimedia processors.
The embedded DRAM allows for some of the key power-saving tricks being tapped by designers today, including sleep mode, partial power cut-off and on-chip temperature compensation, while also improving data retention time.
The 65-nm embedded DRAM process is built on up to 10 metal layers using copper low-k interconnect and nickel silicide transistor interconnect, the company said. The cell size is less than a quarter of its SRAM counterpart, and macro densities range from 4Mbits to 256Mbits.
By: DocMemory
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