The company's Mirrorbit Eclipse architecture is targeted at feature phones and portable multimedia devices, where Spansion believes it can shave 30 percent off the bill of materials compared with a two- or three-chip approach. Spansion will roll first silicon based on 2-bit-per-cell devices in the third quarter and ramp production in early 2008.

But handset designers will reap the greatest benefits when Spansion introduces a hybrid 2-bit/4-bit-per-cell device sometime in early 2009, as it ramps up a 45-nanometer process. Only then will designers be able to play around with the programmability of the memory and determine the advantages of its flexibility.

Basically, Spansion will be offering something akin to a "buy two get one free" special. Here's how it breaks down: Take a 2-Gbit die based on 2-bit/cell MirrorBit technology. For faster code execution, a designer would program that as a 2-bit/cell array. Yet if heavy data storage is also part of the design spec, then half of the die could be mapped as data-centric 4 bits/cell. That would yield an extra gigabit of space for storage of MP3 files, photos or video.

By: DocMemory
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