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TSMC rolls 45-nm process


Monday, April 9, 2007

Taiwan Semiconductor Manufacturing Co. Ltd officially rolled out its 45-nm process technology for foundry customers, with plans to enter production as early as September 2007.

TSMC originally tipped the process last year. The new 45-nm process from TSMC (Hsinchu, Taiwan) combines 193-nm immersion photolithography, strained silicon and ultra low-k inter-metal dielectric material.

TSMC's 45-nm low power process provides twice the density of 65-nm with lower power and manufacturing cost per die. Its 45-nm general-purpose and high-performance process provides more than double the density and a greater than 30 percent speed enhancement over the previous generation at similar leakage power.

With a high-density 6T SRAM cell, more than 500 million transistors will fit into a 70-mm2 die area. In addition, the 45-nm logic family includes a low-power triple gate oxide (LPG) option. All three processes offer multiple threshold voltage (Vt) core devices and 1.8-, 2.5-, 3.3-V I/O options to meet different product requirements.

TSMC has delivered functional chips from its 45-nm multi-project wafer program, dubbed Cybershuttle.

 

By: DocMemory
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