For some time it has been known Intel planned an interconnect known as the Common System Interface (CSI) as a replacement for its processor bus on both Xeon and Itanium lines. However, the company had not revealed details about the interconnect or exactly when it would be used until today.

Intel will use CSI on a 65nm version of the Itanium 2 dubbed Tukwilla that will ship in 2008. It will also roll out high-end versions of Xeon chips and at least one south bridge I/O chip using the interface. The I/O chip will be able to be used in both Tukwilla and Xeon-based systems though it may come in versions that enable or disable certain features depending on the processor.

In the press conference, Intel executives would give no details about CSI other than the fact it will have new features for high reliability. In an interview with EE Times earlier this year an Intel executive said CSI will embrace two different approaches to linking processors in high-end servers.

CSI should enable coherent data transfers between small groups of local processors as well as non-uniform memory links between as many as 128 CPUs over a more widely distributed system. The later capability may require a software abstraction layer to reconcile different levels of memory latency within a system.

Tukwilla will also integrate one or more memory controllers on die. Again, Intel would not detail the controllers except to say they would enable high capacity memories such as one might expect for a large server. They will also enable large symmetric multiprocessing configurations favored by the Itanium.

Intel will skip the 45nm node in its processor line up, to move directly to 32nm for its follow on chip called Poulson. The unusual move can be explained by the fact Intel wants to leapfrog to a position where it can reclaim leadership in process technology with Itanium.

The Itanium line is generally behind its competitors at IBM and Sun Microsystems who now ship top end server CPUs based on 65nm technology. Intel's current Montecito version of Itanium, and even a minor upgrade called Montvale coming later this year still use 90nm technology.

Intel would not give a date for the introduction of Poulson, but managers did say it will not be among the first chips to use Intel's 32nm process. That probably puts Poulson out to at least 2010.

Tukwilla will sport four cores and reincarnate a version of Intel's Hyperthreading technology, which was discontinued in the Xeon line, to process two threads per core. Poulson will have more than four cores and also use dual-threading.

Poulson will also be based on a new microarchitecture. Intel last refreshed the Itanium microarchitecture with the Itanium 2 in 2002.

Executives at the press briefing went to great pains to point out the relatively strong market position for Itanium. Analysts have often speculated Intel might kill the CPU architecture because it ships in such low volumes compared to Intel's x86 line. But Intel notes Itanium is nevertheless a significant and strategic business.

Itanium still trails IBM's Power and Sun's Sparc architectures in overall server revenue, but it is gaining share. Last year in a market for RISC processors that was relatively flat, Itanium sales grew in revenues to about 41 percent the size of those of IBM's Power and 54 percent the size of Sun's Sparc revenues.

By: DocMemory
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