The Brussels-based European Commission-sponsored, and STMicroelectronics-managed project Pullnano is reporting the creation of a functional CMOS SRAM demonstrator built using 32-nm design rules, along with other results related to future-generation 32- and 22-nm CMOS technology platforms.

The consortium explained that since SRAM is required in most of the complex SoC devices that are built with leading-edge CMOS technologies, it believes the demonstration of a functional SRAM is an important milestone.

The functional SRAM was fabricated using MOS transistors whose device architecture differs significantly from that of the transistors used in the 45-nm technology node. Specifically, the transistors were built using a low power consumption approach based on fully depleted silicon on insulator (FDSOI) coupled with a gate stack composed of a high-K gate dielectric and a single metal electrode stack, the consortium said.

Pullnano believes this is the first time that such a compact SRAM cell has been fabricated using FDSOI, high-k dielectric and metal gate together. 

The group said it is ahead of schedule in reaching this milestone and expects to demonstrate an even smaller cell before the end of the year.

Also, as part of the consortium’s back-end-of-line (BEOL) efforts, partners demonstrated that the material and integration schemes used in the 45-nm generation can be modified to provide a robust solution at 32-nm and also proposed a new architecture that could provide even higher performance at 32- and 22-nm, using the so-called “air gap” technique. These results were reported at the IEEE International Interconnect Technology Conference, held last month in San Francisco.

BEOL is the stage in the chip fabrication process when the active components, such as the transistors, are interconnected with metal wiring, Pullnano reminded.

Next, in the field of modeling and simulation, Pullnano academic partners reported development of approaches to predict device performance for the 32- and 22-nm CMOS generations including new simulators that allow the evaluation – ahead of actual fabrication – of the impact of the new technology options such as the channel material and the choice of high-k dielectric.

The selection of the best compromise between physical accuracy and computational effort has led to very efficient and effective ways to account for the quantum mechanical effects which govern the operation of these advanced devices, and the consortium said this work contributes to enriching the standard International Technology Roadmap for Semiconductors device performance evaluation tool.

Gilles Thomas, STMicroelectronics R&D cooperative programs manager and coordinator of the Pullnano project noted that the 32-nm generation “will be a pivotal node for semiconductor manufacturers because we are dealing with layers only a few atoms thick, where quantum mechanical effects become more and more important.”

“The successful industrialization of the 32-nm and 22-nm generations will require a deep understanding of the physical issues as well as the most advanced modeling and simulation tools and the Pullnano consortium is well advanced in developing these,” Thomas added in a statement.

Pullnano is sponsored as part of the 6th Framework Program (FP6) and leverages 38 European partner organizations, including chip manufacturers, research institutions, universities and small and medium Enterprises (SMEs) to develop advanced knowledge meant to allow European chip manufacturers to maintain their strong presence in the worldwide microelectronics industry from 2010, when the 32-nm generation of CMOS technology is expected to be commercially available.

Original Pullnano members include project coordinator STMicroelectronics SA, STMicroelectronics (Crolles2) SAS, NXP Semiconductors Crolles R&D, Freescale Semiconducteurs Centre de Recherche Crolles SAS, NXP Semiconductors Belgium, Philips Electronics Nederland, Infineon Technologies, STMicroelectronics, Commissariat à l'Energie Atomique (LETI), Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung, Swiss Federal Institute of Technology, University of Glasgow, Warsaw University of Technology, Chalmers University of Technology, The University of Liverpool, National Technical University of Athens, National University of Ireland, University of Warwick, The University of Surrey and Qimonda Dresden.

By: DocMemory
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