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Hynix bets on SOI DRAM


Tuesday, August 14, 2007

In a surprising new turn for an emerging memory technology, commodity DRAM manufacturer Hynix Semiconductor has licensed SOI (silicon-on-insulator) DRAM cell technology from startup Innovative Silicon. The move is startling both because it puts a massive company firmly in Innovative's camp and because Hynix intends to use the technology not for embedded DRAM in systems-on-chip—Innovative's original application target—but for a new generation of bulk DRAM chips.

The agreement, according to Jeff Lewis, Innovative's vice president of marketing, includes both a technology license and an engineering joint development. "We are not disclosing the exact terms, but it is an eight-figure agreement comprising an engineering fee, a license fee, and royalties," he said.

Much of the collaboration between the two engineering teams will involve moving Innovative's unique one-transistor dynamic memory cell from the SOI logic processes in which it has previously been implemented to an SOI version of Hynix's memory process. This change will involve both introducing SOI to Hynix and porting the floating-body memory cell to a process that is rich in poly layers and has very fine contact pitch but is relatively poor in metal interconnect

The potential payoff for Hynix would be a substantial technical differentiation—something very hard to come by in the DRAM business. "Today, about 20% of the area of a DRAM chip is taken up by the storage capacitors," Lewis observed. "And a large number of process steps go just to forming the capacitor structures. Eliminating the capacitors means reducing the die area and shortening the process time, both of which have immediate financial implications." In addition reasons exist to believe that the floating-body technology will scale better than capacitor-based DRAM at finer geometries, although predictions of the end of capacitor scaling have proved wrong many times before.

The agreement raises an immediate question: Is the supply of SOI wafers sufficient? At the moment, the dominant supplier is Soitec, which has a nearly complete fab complex in France and another under construction in Singapore. Even with both facilities operating, a ramp-up of DRAM production at Hynix could tax the global supply of SOI wafers, which must be fabricated from silicon wafers in a multistep process. Further questions would arise if events at AMD resulted in a temporary drop in SOI wafer demand between now and the presumed Hynix production startup date, possibly constraining funds for completion of the Singapore facility.

The Innovative Silicon technology works by turning one of the demons of SOI circuit design, the floating-body effect, into a useful tool. Floating-body effect occurs when normal channel current drives charge into the isolated thin layer of silicon—the floating body—beneath the channel of an SOI MOSFET. The charge becomes temporarily trapped there and alters the threshold voltage of the transistor.

In ordinary circuit design this is a serious problem, because it makes the behavior of the transistor dependent on its recent switching history. A transistor that has been in the off state for some time may have a quite different threshold voltage than one that has been switching rapidly. Consequently logic designers work both to minimize the effect through changes in transistor design and to reduce the effect's impact on timing through circuit-design measures.

By contrast, Innovative Silicon aims to maximize this stored charge and use it to store information. By re-engineering the transistor, Innovative has succeeded in maximizing, rather than minimizing, the floating-body effect. Normal-looking read cycles can predictably alter the charge in the floating body, in effect setting the transistor to a 1 or 0 state. When a write cycle turns on the transistor, sense amps see a significant difference in current between a 1 and a 0 bit. The result is a dynamic storage element comprising a single transistor with no separate capacitor structure, a large current margin between 1 and 0 states, and a retention time comparable to that of conventional DRAMs.

By: DocMemory
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