In an effort to make it easier for IC designers to create interoperable SystemVerilog verification flows, Cadence Design Systems and Mentor Graphics today announced that they have jointly created—and will standardize on—a free, open-source verification methodology called OVM (Open Verification Methodology).

According to the companies, OVM will allow chip designers and third-party providers of VIP (verification IP) to create testbenches and models in one format that will run in any OVM-compliant tool environment.

Up until this point, each EDA vendor offering SystemVerilog simulation flows has developed its own guidelines that users must adopt to develop VIP for particular design flows, according to Steve Glaser, corporate vice president of marketing in the verification division at Cadence, and Dennis Brophy, Mentor's director of strategic business development. Mentor has offered the AVM (Advanced Verification Methodology) and Cadence has offered its own format called UVM (Unified Verification Methodology).

"Our customers have noticed that we've continued down this path of using our own proprietary, company-centric methodologies because they have to support N number of ways of doing things on N×N number of tools, which is making their job of porting verification information a challenge," Brophy said. "What we have been doing is hampering design collaboration, because as one team finishes what they are doing—finishes a block or project they've been working on—they then need to integrate that into their overall design. Each group may be using a different vendor's tool and using different methods. And it may be that multiple companies are collaborating on a design, but today they can't easily port verification IP back and forth."

Today, for example, if a user develops a piece of VIP, such as a SystemVerilog testbench, a transaction-level model, or an RTL model using one vendor's format, that VIP would not easily work in the other vendor's SystemVerilog simulation environment. "Users would essentially have to do the work themselves and build a bridge between the two vendors' environments to make the VIP work in the other's tool environment," Brophy said. "The new OVM will eliminate the need for users to create that bridge on their own. What we are doing is enabling a truly interoperable verification IP environment, promoting language interoperability, and enabling data portability across multiple simulator platforms to deliver on the promise of SystemVerilog and open up a very healthy and vibrant design and verification community."

OVM is actually a superset of AVM and UVM, and both Cadence and Mentor dedicated developers to combining the best of both worlds in OVM. The OVM deliverables include the OVM Methodology, which consists of how-to documentation, examples, and code snippets, and an OVM class library—essentially the building blocks to develop VIP.

"We tried to look at this problem quite holistically," Glaser said. The companies realized that to enable the OVM, they needed to not only standardize on an open set of functional building blocks, called class libraries, but also address larger concerns. "There are a lot of methodological implications that then connect into even higher-level library functions, and then even into the way tools need to interpret data, and then the way customers need to take IP from different sources and configure it for different parameters and then start operating it, controlling it, and being able to get messages back," Glaser said. "There are a lot of considerations for plug-and-play IP from multiple sources, as well as the path from block- to chip- to system-level reuse, which tends to bring in other languages such as SystemC." Brophy and Glaser claim OVM addresses all these issues and is completely compliant with IEEE OpenVerilog language standard 1800-2005.

At least initially, the new methodology is a direct competitor and a competitive response to Synopsys' proprietary VMM SystemVerilog guidelines, which are also compliant with IEEE 1800-2005. Synopsys has been a strong proponent of SystemVerilog, and some would say the company has been the frontrunner in the space ever since it acquired the company that originally developed SystemVerilog, Co-Ware Design Automation, a few years ago.

But, the VMM, according to Glaser and Brophy, has been less than open and has lacked significant links into SystemC (SystemVerilog and SystemC were seen as competing languages when they were introduced a few years ago). Both Brophy and Glaser said that Synopsys has in the past declined to join any open SystemVerilog efforts. Synopsys and all other vendors are free to adopt the OVM at any point, they said.

Certainly, broad adoption of a single, viable SystemVerilog methodology would help designers use their multivendor SystemVerilog tool flows and would likely increase the usage and sales of SystemVerilog tools and methods. "We think OVM will be a great step toward speeding up the adoption of SystemVerilog and advanced verification methodologies," Glaser said. "We think it will be very well received by the user community and move to 100% adoption very quickly."

Both companies had to make modifications to their respective SystemVerilog simulation environments so that they could run VIP created using the OVM guidelines, Brophy said. Now each company has verified that its simulation platform (Mentor's Questa and Cadence's Incisive) can run VIP created with the OVM guidelines. Making the tools OVM-compliant wasn't a painstaking process, Brophy noted, so it should be fairly easy for other vendors to follow suit with their own tools.

Cadence and Mentor are offering OVM as a free, open-source license called Apache 2.0. The companies will initially offer the license to select customers in the third quarter of this year. After working out any kinks, they plan to make a full production release, including the methodology and supporting library, in the fourth quarter.

Initially, the companies will make Apache 2.0 available for download from their existing Web sites. However, plans are in the works to build a dedicated OVM site. Brophy, who is also an officer at standards group Accellera, noted that if the OVM collaboration effort takes off and develops any software deliverables, the OVM group may want to move the effort to that organization.

By: DocMemory
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