The technology utilizes a silicon controlled rectifier (SCR) design to reduce leakage current and ensure adequate ESD protection without compromising performance. The leakage current has been reduced by approximately 4 decades to 1.0 nA, while the trigger voltage of 1.8 V was about 60 percent lower, according to NEC.

The new technology is suited for use in high-speed interface circuits for standards such as PCI Express and Serial ATA.

Because of the shrinking geometries of devices at the 65-nm node and smaller, voltage and current tolerances at the circuit level have become ever more stringent. But smaller geometries require the same level of ESD protection as larger ones, according to NEC.

NEC has previously developed SCR-type ESD protection circuits using N-channel MOSFET in the trigger element. "These circuits have the advantages of small size and low parasitic capacitance," according to the company. "However, it was difficult to reduce leakage current during normal operation while at the same time lowering the trigger voltage during ESD events."

The new technology uses a P-channel MOSFET for the trigger element and an enhanced design for the connection between the trigger element and SCR.

The trigger element in the new technology is a P-channel MOSFET with four terminals (drain, gate, source, and backgate). ''It is designed so that the potential of the source terminal is lower than that of the gate and backgate terminals, which makes it possible to significantly reduce the current flowing into the trigger element,'' according to NEC.

By: DocMemory
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