Delays between microprocessors and external DRAMs have long been a bottleneck in system performance. "Today the memory bandwidth requirements are going up dramatically due to multicore processors running multiple threads per core," said Kevin Donnelly, a senior vice president of engineering at Rambus.

Attacking this problem, Rambus will demonstrate multiple memory channels running at up to 16 Gbits/s each, about four times faster than individual channels currently in development. The Tokyo demonstration is expected to show a 65nm controllerr linked to two 65nm RAM devices with aggregate throughput of up to 32 Gbytes/s to each memory chip.

Rambus will achieve that throughout by applying three signaling techniques to relatively traditional discrete devices. The controller is in a flip-chip package and the RAMs use wire bonding.

"Our intention is to show something that is realistically manufacturable a few years out," said Steve Woo, a technical director at Rambus. "It would not be unreasonable to see this need [for a Tbyte/s memory chip] in 2010 or 2011," he added.

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved