Hsinchu, Taiwan-based Taiwan Semiconductor Manufacturing Co. detailed today that it has developed what it believes is the first 32 nm technology that supports both analog and digital functionality, during a paper presentation at the IEEE International Electron Devices Meeting in Washington, D.C.

TSMC said it has proven the full functionality of a 2Mb SRAM test chip with the smallest bit-cell at the 32 nm node, which is optimized for low power, high density and manufacturing margins with optimal process complexity and calling attention to the fact that this is the first 32 nm low-power technology that did not have to resort to high-k gate dielectric and metal gates to achieve its performance characteristics.

Yesterday, IBM, following its 45 nm high-k/metal gate work it promoted in January, announced with partners the move to high-k/metal gate in 32 nm with SRAM and silicon-on-insulator (SOI) technologies.

Low power technology integrated with high density SRAM, low standby transistors, analog and RF functions, and copper and low-k interconnects are ideal for SoC devices targeted in mobile applications, TSMC reminded. The company also said it plans to provide complete digital, analog and RF functions, and high density memory capabilities at the 32 nm node.

In addition, TSMC pointed out that a 0.15-micron high density SRAM cell has been realized by 193 nm immersion lithography using double patterning approach.

In other TSMC news, the company also said today that semiconductor design tool supplier Synopsys Inc. has qualified its Star-RCXT parasitic extraction tool for TSMC's 45 nm process technology, thanks to collaboration between Synopsys, Altera and TSMC to develop and silicon-validate advanced modeling of key process variation effects that impact the performance of digital, analog and memory circuits.

Programmable logic supplier Altera said it is deploying Synopsys' Star-RCXT as the preferred extraction tool for its 45 nm design sign-off flow.

Hsinchu, Taiwan-based Taiwan Semiconductor Manufacturing Co. detailed today that it has developed what it believes is the first 32 nm technology that supports both analog and digital functionality, during a paper presentation at the IEEE International Electron Devices Meeting in Washington, D.C.

TSMC said it has proven the full functionality of a 2Mb SRAM test chip with the smallest bit-cell at the 32 nm node, which is optimized for low power, high density and manufacturing margins with optimal process complexity and calling attention to the fact that this is the first 32 nm low-power technology that did not have to resort to high-k gate dielectric and metal gates to achieve its performance characteristics.

Yesterday, IBM, following its 45 nm high-k/metal gate work it promoted in January, announced with partners the move to high-k/metal gate in 32 nm with SRAM and silicon-on-insulator (SOI) technologies.

Low power technology integrated with high density SRAM, low standby transistors, analog and RF functions, and copper and low-k interconnects are ideal for SoC devices targeted in mobile applications, TSMC reminded. The company also said it plans to provide complete digital, analog and RF functions, and high density memory capabilities at the 32 nm node.

In addition, TSMC pointed out that a 0.15-micron high density SRAM cell has been realized by 193 nm immersion lithography using double patterning approach.

In other TSMC news, the company also said today that semiconductor design tool supplier Synopsys Inc. has qualified its Star-RCXT parasitic extraction tool for TSMC's 45 nm process technology, thanks to collaboration between Synopsys, Altera and TSMC to develop and silicon-validate advanced modeling of key process variation effects that impact the performance of digital, analog and memory circuits.

Programmable logic supplier Altera said it is deploying Synopsys' Star-RCXT as the preferred extraction tool for its 45 nm design sign-off flow.

By: DocMemory
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