Tuesday, March 25, 2008
TSMC announced its first 40 nm manufacturing process technology that includes a full design service package and a design ecosystem that covers verified third party IP, third party EDA tools, TSMC-generated SPICE models and foundation IPs.
First wafers out are expected in Q2.
Highlights of TSMC’s 40 nm process technology include a 2.35 times raw gate density improvement over its 65 nm process technology; active power down-scaling of up to 15% over its 45 nm process technology; what the company believes is the smallest SRAM cell size and macro size in the industry; general purpose and low power versions for broad product applications; dozens of customers projects in the design pipeline today; and frequent and regular CyberShuttle with MPW prototyping running.
The company reminded that it has moved forward quickly to develop enhanced 40 nm low power (40LP) and 40 nm general purpose (40G) processes in order to deliver high performance with 40 nm density following successful tapeouts and customer announcements with its 45 nm process technology last year.
TSMC’s 45 nm node allowed double the gate density of its 65 nm manufacturing technology, while the 40 nm node contains manufacturing innovations that allow its LP and G processes to deliver a 2.35 raw gate density improvement of the 65 nm offering with the transition from 45 to 40 nm low power technology allowing a reduction of power scaling up to 15%.
John Wei, senior director of advanced technology marketing at TSMC explained in a statement, “Our design flow can take designs started at 45 nm and target it toward the advantages of 40 nm. A lot of TSMC development work has gone into ensuring that this transition is truly transparent. Designers need only concentrate on achieving their performance objectives.”
Specifically, the 40LP technology was developed for leakage-sensitive applications such as wireless and portable devices, while the 40G variant targets performance applications including CPU, GPU, game console, networking and FPGA designs and other high-performance consumer devices.
The 40G and LP processes will initially run in TSMC's 12" wafer Fab 12 and will be transferred to Fab 14 as demand ramps, the company concluded.
By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved
|
