Altera Corp announce a new family of 40-nanometer FPGA  also known as HardCopy IV structured ASICs, as well as corresponding software tools for both device types.

Fabricated in Taiwan Semiconductor Manufacturing Co. Ltd.'s 40-nm foundry process, the families promise to enable a new class of single-chip, multicore and related complex devices.

Altera has been talking in general terms about 40-nm FPGAs for some time, though a source at Xilinx speculated Altera has been pumping up the 40-nm development to deflect attention from the lackluster market for its 65-nm lineup.

Altera is expected to ship the first of its 40-nm FPGAs by the end of the year. One of its two foundry partners, United Microelectronics Corp. (UMC), is expected to ship its initial 45-/40-nm wafers by year's end. Xilinx's other foundry partner, Toshiba , claims to be in 45-nm logic production.

Altera offers PLDs as well as ASICs and FPGAs, viewing the categories as complementary. Designers can use Altera's HardCopy methodology to develop a prototype on an FPGA, then move into production with a structured ASIC. Greenfield said the 40-nm technology will enable a new class of system-level products.

The devices to be announced today include 12 entries in the Stratix IV FPGA line and 12 in the HardCopy IV structured-ASIC family. The Stratix IV is said to have twice the density of the company's 65-nm Stratix III. One Stratix IV entry supports up to 48 transceivers operating at up to 8.5-Gbits/second.

The Stratix IV FPGAs have a core performance of 350 MHz, identical to that of the Stratix III devices, but add new hard IP blocks to enhance performance. Both the 65- and 40-nm families contain DSP and memory blocks that run in excess of 550 MHz, as well as PCI Express hard IP blocks running at 500 MHz. Like the 65-nm versions, the Stratix IV devices feature Altera's Programmable Power Technology, which optimizes logic, DSP and memory blocks to help manage static power, Greenfield said.

The Stratix IV comprises two lines: an enhanced memory/DSP offering (Stratix IV E) and a variant with transceivers (Stratix IV GX). The top entry in the GX line has 530,000 logic elements, 48 transceivers, 20.3 Mbits of memory and 1,024 18 x 18 multipliers. The high-end E entry has 680,000 logic elements, 22.4 Mbits of memory and 1,360 18 x 18 multipliers.

The HardCopy IV ASIC family offers equivalent densities to the Stratix IV devices and features up to 13.3 million gates. For the first time, Altera is offering a transceiver-based ASIC option with HardCopy IV.

The new Quartus II software v.8.0 delivers, on average, three times the compile speed for high-end FPGAs compared with the nearest competitor's latest offering, according to Altera.

Engineering samples of the first Stratix IV entry are slated for the fourth quarter.

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved