A paper to be presented at the SIGGRAPH 2008 conference in Los Angeles on Aug. 12 includes details of a new approach to the software rendering 3-D pipeline, a many-core (many processor engines in a product) programming model and performance analysis for several applications.

According to the first product based on Larrabee will target the personal computer graphics market and is expected in 2009 or 2010. Larrabee will be a many-core x86 Intel architecture based on an array of many processors similar to existing processors.

Intel says it has a number of internal teams, projects and software-related efforts underway to speed the transition, but the tera-scale research program has been the single largest investment in Intels technology research and has partnered with more than 400 universities, DARPA and companies such as Microsoft and HP to move the industry in this direction.

The Larrabee architecture is predicted to bring about massive innovation in many areas and market segments such as games which traditionally work within a rigid and limited framework. Intel believes Larrabee will give developers of games and application programming interface for a 'blank canvas'.

Initial product implementations of the Larrabee architecture will target discrete graphics applications, support DirectX and OpenGL, and run existing games and programs. Additionally, a potential range of highly parallel applications including scientific and engineering software will benefit from the Larrabee native C/C++ programming model.

The paper at SIGGRAPH, titled Larrabee: A Many-Core x86 Architecture for Visual Computing, will describe how the Larrabee architecture has a pipeline derived from the dual-issue Intel Pentium processor, which uses a short execution pipeline with a fully coherent cache structure. The architecture provides enhancements such as a wide vector processing unit (VPU), multi-threading, 64-bit extensions and sophisticated pre-fetching. This will enable a massive increase in available computational power combined with the familiarity and ease of programming of the Intel architecture.

Larrabee also includes a select few fixed function logic blocks to support graphics and other applications. These units are carefully chosen to balance strong performance per watt, yet contribute to the flexibility and programmability of the architecture. A coherent on-die 2nd level cache allows efficient inter-processor communication and high-bandwidth local data to be access by CPU cores, making the writing of software programs simpler.

The Larrabee native programming model supports a variety of highly parallel applications, including those that use irregular data structures. This enables development of graphics APIs, rapid innovation of new graphics algorithms, and true general purpose computation on the graphics processor with established PC software development tools.

The architecture features task scheduling which is performed entirely with software, rather than in fixed function logic. Therefore rendering pipelines and other complex software systems can adjust their resource scheduling based each workloads unique computing demand.

It supports four execution threads per core with separate register sets per thread. This allows the use of a simple efficient in-order pipeline, but retains many of the latency-hiding benefits of more complex out-of-order pipelines when running highly parallel applications.

It uses a 1024 bits-wide, bi-directional ring network (i.e., 512 bits in each direction) to allow agents to communicate with each other in low latency manner resulting in super fast communication between cores.

The Larrabee architecture fully supports IEEE standards for single and double precision floating-point arithmetic. Support for these standards is a pre-requisite for many types of tasks including financial applications.

By: DocMemory
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