The 50-nanometer circuit technology enables the use of up to 8 GB of memory chips for RIMMs, or registered in-line memory modules, without the need of stacking components, Samsung said. The technology also enables the use of 4 GB for SODIMMs, or small outline dual in-line memory modules, and UDIMMs, or unregistered in-line memory modules. In addition, 2-Gb DDR3 RIMMS can be designed to 16 GB by applying dual-die packages.

In building the latest 2-Gb module, Samsung "focused on maximizing density alternatives and power savings to make our 2-Gb DDR3 solution as flexible as possible for designers," Jim Elliott, VP of memory at Samsung Semiconductor, said in a statement.

The latest chip is an alternative to having two 1-Gb memory devices. The larger memory module can be used to build memory chips that use at least 40% less power than dual-chip products, Samsung said. The 2-Gb device supports a data rate of up to 1.3 Gbps at 1.5 or 1.35 volts, making it up to 1.6 times faster than an 800-Mbps 1 Gb-based dual-die package. In addition, the reduced number of DDR3 chips lowers heat emissions.

Samsung plans to make its 50-nm manufacturing process its primary DRAM fab technology next year. Mass production of the latest module is scheduled to begin before the end of this year. Samsung started volume production of 50-nm 1-Gb DDR2 modules in April.

DDR3 is expected to increase from 29% of the DRAM market in terms of units sold to 72% by 2011, according to IDC. The 2-Gb device segment is expected to grow from 3% to nearly a third by 2011.