Thursday, December 18, 2008
Toshiba, IBM and AMD have developed what they says is the smallest functional SRAM cell that makes use of FinFETs. The trio outlined details of the cell at this week's International Electron Devices Meeting in San Francisco.
The cell, developed with a high-k/metal gate (HKMG) material, has an area of 0.128µm2, is said to have significant advantages over planar-FET cells for future technology generations.
The collaborators optimized the processes, especially for depositing and removing materials, including HKMG from vertical surfaces of the non planar FinFET structure.
The researchers also say the design is likely to scale to the 22-nm node or beyond, and that the nonplanar-FET SRAM cell is more than 50 percent smaller than the 0.274¼m2 such cell previously reported.
The trio also investigated the stochastic variation of FinFET properties within the highly scaled SRAM cells and simulated SRAM cell variations at an even smaller cell size. They verified that FinFETs without channel doping improved transistor characteristic variability by more than 28 percent.
In simulations of SRAM cells of 0.063¼m2 area, equivalent to or beyond the cell scaling for the 22nm node, the results confirmed that the FinFET SRAM cell is expected to offer a significant advantage in stable operation compared to a planar-FET SRAM cell at this generation.
By: DocMemory
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