From the deluge of fine papers at the International Electron Devices Meeting last week it is possible to see the outlines of a broad movement within the design community: development to provide the necessary process technology for the 32- and 22-nm generations of DRAM cells. This development, progressing around the globe, encompasses materials, process integration, and device design efforts.

One case in point is the effort to continue scaling of DRAM. A number of advanced but not yet proven technologies, such as phase-change memory, offer to replace the DRAM cell as the industry's ability to scale the tiny device runs out. But major effort is also going into keeping the capacitor-based DRAM cell in the picture.

A paper from NEC, for example, describes a revamping of the planar CMOS transistor to attack the problems of the tiny transistor inside the DRAM cell. This issue is of pivotal importance to NEC because many of the company's advanced CMOS products—both internal and through its ASIC group—depend on embedded DRAM.

As the cell gets smaller, the transistor necessarily gets smaller. But scaling the cell transistor into the 32-nm realm requires very shallow junction depths. That, in turn, creates problems with both high source-drain resistivity and high junction leakage.

In an elegant series of modifications to the planar MOSFET, NEC engineers described creating a raised-source/drain device to decrease resistivity while at the same time shaping the crystal surfaces of the channel region to reduce capacitance between the channel and the source and drain regions. They also explained novel annealing and dual-diffusion approaches that substantially reduce junction leakage. The result, according to Hirohito Watanabe, general manager of NEC's LSI Fundamental Research Lab, is a 32-nm MOSFET using conventional materials but with 30% lower operating power than a conventional device of that size—translating into both lower array power and longer data retention—and no appreciable increase in short-channel effect. Along with being a significant demonstration in elegant device design, the work shows that the planar MOSFET may have several generations left in it as device designers learn to control even the finest details of the transistor.

While NEC works on the cell transistor, European research consortium IMEC is working on the cell capacitor. Scaling is running the current capacitor dielectric materials out of business. We have tried drilling into the wafer to make a trench, and building up from the wafer to make a tower, but there is simply no longer a way to get enough capacitor area packed into the tiny three-dimensional space available for a DRAM cell. We need a higher-k dielectric material.

One IMEC paper presented at IEDM directly addresses this issue, describing work with strontium-titanium-oxide dielectrics to reduce the required capacitor area for the DRAM cell. A team including researchers from IMEC, academia, and ASM described using atomic-layer deposition of SrTiO₃ on a relatively common TiN electrode to create metal-insulator-metal (MIM) capacitors with equivalent oxide thickness (EOT) of below 0.5 nm and low leakage. The paper claimed record values for leakage and EOT. The work required delicate adjustment of the deposition process and the precursor materials to achieve precise structure in the insulator.

By: DocMemory
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