The two papers raised the question of whether the future of microprocessors will be down the system-on-chip or system-in-package road. While that issue gets debated, Intel's dominance in microprocessors is increasingly apparent.

Intel supplied four of eight papers at the session where NEC's paper was the only other to generate a buzz. "It was a dry year," said Krste Asanovi, a computer science associate professor at Berkeley.

The gap between Intel and its rivals Advanced Micro Devices, IBM and Sun Microsystems is expected to widen. One rival remarked with amazement that, despite the deep recession, Intel still plans to ship 32 nm CPUs in 2009.

"We probably will not do that until 2011," said the engineer who asked not to be named.

In one of its papers Intel described Nehalem-EX, a 2.3 billion transistor server CPU, a member of its 45 nm Nehalem family expected to ship this fall. The chip includes eight cores supporting dual threading, two memory controllers and four 6.4 GigaTransfer/second point-to-point interconnects to create direct links between multiple CPUs in a high-end server.

The architecture mirrors that of archrival AMD which integrates memory controllers and the HyperTransport interconnect on its CPUs. Intel's QuickPath Interconnect (QPI) is "the biggest platform change Intel has made in 10 years," said Rajesh Kumar, an Intel architect who gave a separate paper on the Nehalem family.

Intel spent much of its time discussing its techniques for low power consumption on processors such as the Nehalem-EX which dissipates up to 130 W. The processor uses three separate voltage and clock domains to optimize control of its cores, I/O and non-core areas. It can also disable unused QPI ports in idle power to save on average about 2W per disabled port.

Nehalem also marks a shift away from fast domino circuits used for the previous CPUs to more power efficient static circuits.

"In the 1990's our focus was on performance at all costs," said Kumar. "We built circuits that were inherently faster, but they were burning a lot of power for small gains. With Nehalem we could not afford that anymore," he added.

A paper presented by Hideaki Saito, a principal researcher at NEC, suggested it's time to move to system-in-package technology for processor memory, at least for complex chips used in devices such as smart phones.

Saito described a technique for stacking a memory chip and mobile processor using direct aluminum-to-copper links. The memory chip is based on a 2-D array of SRAM cells that can be configured to link with various logic blocks based on the needs of a given application.

NEC researchers created a novel network interconnect for the stack. It also developed a unique 10-micron pitch electrode to link the two die.

The company created a prototype chip using a Mbit-class memory array fabricated in a 90 nm process and linked to a processor chip via 3,269 electrodes. The links had a 93 picosecond delay.

Saito claimed the approach would deliver fast memory access. It also lets chip makers fab memory and processor die in separate processes to save cost.

"I think it is very promising, but I would not use the reconfigurability because it would add more latency," said one processor designer who attended the session but asked not to be named.

Asanovi of Berkeley said he thought the approach would be too costly, especially if the interconnect scheme introduced yield problems. "It's just a research project," he said.

Indeed, Saito said it would be at least two years before his work might be applied to commercial product.

By: DocMemory
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