Tuesday, July 14, 2009
Chartered Semiconductor Manufacturing has rolled out separate low-power and RF processes, based on its 65-nm technology.
The process is said to utilize leakage-reduction techniques to improve system-on-chip (SoC) standby power consumption by up to 50 percent.
The process improves the performance-to-leakage ratio within the pMOSFET. Given the same Ion the Ioff current is reduced by a magnitude of 20X, according to Chartered.
Chartered's new process features a core 25 angstrom transistor oxide with three voltage options (standard Vt, low Vt, high Vt). The high Vt option offers the lowest leakage at 0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors, respectively.
Two thick gate oxides are available: a 32A device for 1.8V; and an IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length.
The back-end-of-line (BEOL) metal implementation supports up to nine layers of copper to optimize die size and efficiency. Manufactured on rotated substrates, the 65LPe process benefits from the an increase in the pMOSFET hole mobility and saturation velocity without affecting the nMOSFET.
A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic.
By: DocMemory
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