As if it wasn't enough to hear about process development directly from an Intel engineer who has been there through the transition from metal to poly gates and back again, this time I also was fortunate to have Sanjay Natarajan on hand to add details and answer my questions. Natarajan is Intel's 32-nm program manager charged with keeping his node rolling ahead of schedule.

The latest Intel briefing provided some news in advance of the 2009 Intel Developer Forum (IDF) beginning Sept. 22 in San Francisco. I expect Intel will announce the launch or at least the launch date for the first chips from the Westmere 32-nm family of processors during IDF.

Intel's PR team had two more reasons for holding analyst calls last week. One was to announce two papers that will be presented at IEDM in December. The second, but more significant, is that 32-nm production wafers are now moving through Intel's D1D fab in Oregon.

I have not yet deciphered the code for what is happening here, but these wafers are said to be "in support of planned Q4 revenue production." If you take that at face value, then Intel should be shipping 32-nm processors to customers before the end of the year.

However, none of the people I talked to at Intel were willing to commit to that deadline despite widespread assumptions that they will. That's why I suspect important announcements will be made next week since there is no reason to believe product shipments would be delayed at this point.

One IEDM papers describes the 32-nm process which is Intel's second generation of high-k metal gate (HKMG) technology. Paul Packan will present "32-nm Technology for High Performance CPUs." Natarajan said Intel's presentation will provide more process details than past conference papers.

For now, we know that Intel has improved NMOS drive current by 19 percent and PMOS by a whopping 28 percent compared to the 45-nm node. As Bohr pointed out, designers have desired balanced NMOS and PMOS performance ever since Intel rolled out its first CMOS process in 1981. Perhaps, as he said, we are getting closer to that dream.

Intel process engineers also boosted 32-nm PMOS transistors saturation currents closer to NMOS by virtue of the fact that, as Sanjay put it, "There are more knobs to turn in the PMOS process flow." Since embedded SiGe source/drains strain the PMOS channels to enhance hole mobility, in addition to using stress liners deposited after the gates, the PMOS devices employ additional strain enhancement techniques compared to NMOS transistors. Bohr reminded me that the replacement gate flow used by Intel also benefits PMOS transistor performance.

Jumps in drive current--especially the PMOS--are a big achievement, but Intel also wants to get the word out about the leakage performance of their 32-nm transistors. Record-breaking saturation current is nothing new for Intel, but they can now add the best reported leakage to their list of achievements. The design flexibility of trading off leakage for drive current has been part of Intel presentations for some time.

The range of transistor performance matching application has been growing as technology nodes shrink. Intel also said its yield ramps are getting faster at each node.

Perhaps the biggest news surrounding Intel's 32-nm process is the introduction of immersion lithography. The new tools are used on critical layers up to metal three to provide Intel with another best: the smallest contacted gate pitch of 112.5 nm.

Even 28-nm processes in the literature cannot top that dimension.

The second IEDM paper describes the 32-nm SoC process. The transistor performance range offered in the new process provides several advantages for non-CPU applications. That could well be the real story of the Intel 32-nm process, but one I will save for later.

By: DocMemory
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