Monday, January 25, 2010
Since the announcement of the first 56-nm three-bit-per-cell 16-Gbit NAND technology in 2008 by SanDisk and Toshiba, the NAND industry has been working to commercialize this multibit-per-cell technology. Technological challenges associated with process node migration and the economic condition of the NAND flash market (oversupplies and declining prices) has accelerated the development of multibit-per-cell technologies such as three bit per cell (3bpc) and even four bit per cell (4bpc).
Since SanDisk and Toshiba's announcement of 3bpc technology in 2008, several more announcements have occurred in both 3bpc and 4bpc NAND flash technologies. 2009 was the year of 3bpc and 4bpc technology and product introductions, as Table 1 shows. All the major NAND manufacturers introduced or announced their technology and products in an effort to achieve more production efficiency.
Table 1: Summary of three-bit-per-cell and four-bit-per-cell NAND flash announcements
| The efficiency trends of various NAND flash technologies ranging from SLC, MLC, 3bpc and 4bpc technology across several process node generations are shown in Figure 1. The efficiency improvements shown in 4x-nm and 3x-nm process node generations are combined results of process node migration and three- and four-bit-per-cell technology.
Figure 1: Efficiency trends for NAND flash across process nodes and multibit technologies
| For example, at 43-nm process node generation, four NAND flash products/ designs are introduced. By comparing their Mbit per mm2 figures, you can see the impact of 3pbc and 4bpc technology (shown in Table 2.
Table 2: Efficiency comparison of 43-nm NAND flash technologies
| Three-bit-per-cell technology improves NAND flash efficiency dramatically without introducing a new process node: based on 32-Gbit NAND example, the efficiency improvement of 3bpc technology is around 31 percent. This is close to the efficiency improvement effect of migrating to the next process node. By introducing 3bpc NAND technology, the NAND industry is able to reduce chip size and improve productivity without the investment and heavy R&D efforts required to migrate to more advanced process node technology.
Products introduced in 2009 using 3bpc NAND technology include microSDHC memory cards and memory sticks. Given the requirement of sophisticated program, erase and read algorithms of 3bpc technology and extended error correction, these memory cards, which have NAND flash controllers inside, are better suited for commercial application of 3bpc NAND technology.
At UBM TechInsights, we have begun analyzing the industry-leading 3bpc manufacturer SanDisk's 43-nm 3bpc 32-Gb NAND flash found in the SanDisk memory card. We're examining the detailed circuit of the NAND flash memory array and its associated blocks such as page buffers and wordline switches. We also plan to perform a waveform analysis of the NAND to dissect the programming, reading and erase operation of the 3bpc operation.
Also being analyzed by UBM TechInsights is the Intel Micron's 32-nm 3bpc 32-Gb NAND flash. Again, we're analyzing the detailed circuit of the NAND flash memory array and its associated blocks such as page buffers and wordline switches.
Based on initial analysis of the 3bpc NAND flash devices, we have quantified the die-area-reduction effect of 3bpc technology. With 50 percent more bit storage capacity than MLC (multibit per cell or two bit per cell), 3bpc NAND technology can reduce NAND array areas around 33 percent and overall chip size by 18 percent to 25 percent depending on the density.
As shown in Table 3, higher-density designs benefit more due to the overhead circuitry shared by more bits. To maximize 3bpc technology's benefits, NAND products using this technology should be at least 32 Gbits or higher.
Table 3: Array and chip size reduction of three-bit-per-cell technology
| According to SanDisk, more than 50 percent of bit production was in 3bpc or 4bpc in the third quarter of 2009. SanDisk also expressed that their X3 technology (3bpc technology) is applied across all of SanDisk product platforms. It is expected that SanDisk's X3 technology will be the workhorse technology in 2010. Some concerns have cropped up about the performance of 3bpc-based NAND flash given the complicated programming algorithms and high degree of error correction. SanDisk, however, claims that the performance of X3 and X4 is essentially identical to MLC (X2 or two bit per cell) and maintains identical pricing between X2, X3 and X4.
Industry sources predict that the adoption of 3bpc NAND in the memory card market will be fast expanding in 2010. Some predict that 70 to 80 percent of two-bit-per-cell chips used in entry-level flash drives and memory cards will be replaced by 3bpc ones in 2010. This year many more 3x-nm NAND flash products using 3bpc technology will be introduced supporting development of more cost-competitive, high-density consumer electronics storage solutions.
As the NAND industry had successfully introduced and commercialized MLC technology several years ago, three-bit-per-cell technology will help the NAND industry produce efficient nonvolatile storage fueling growth of many current and new applications.
By: DocMemory
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