FPGA vendor Altera Corp. plans to introduce several innovations for its first 28-nm chips, including partial reconfiguration, 28-gigabit-per-second (Gbps) transceivers and embedded hard intellectual property (IP) blocks, the company announced Monday (Feb. 1).

Altera (San Jose, Calif.) has said it intends to have 28-nm FPGAs available this year. However, the company has not disclosed a specific target date for their introduction.

According to Altera, the partial reconfiguration capability on its 28-nm chips will enable customers to load new functionality into portions of the FPGA without interrupting normal operation. Users will benefit from reduced cost and power consumption by implementing only active logic, the company said. Partial reconfiguration will all enable customers to implement system enhancements remotely, without disrupting the FPGA's operation, the company said.

Luanne Schirrmeister, senior director of product marketing at Altera, said partial reconfiguration is not a new concept, though this is the first time Altera has attempted to offer it. It's never really gained much traction, Schirrmeister said, partly because using it required customers to learn all the intricate architectural details of a device.

"What we are going to do that is different," Schirrmeister said. "We are going to built partial reconfiguration as a natural extension of our functional design flow." The capability will be built on top of the incremental compile design flow in its Quartus II design software, she said.

Rich Wawrzyniak, an analyst with Semico Research Corp., described Altera's partial reconfiguration technology as a real step forward for the programmable logic market. "Yeah, it's going to require people to really understand their application and think long and hard about what they are going to do," Wawrzyniak said." But if you can do that, what they've provided here is going to allow people to come up with some real innovative stuff."

Xilinx Inc. has for several years offered a technology called active partial reconfiguration on several of its FPGAs. A spokesperson for Xilinx said the company is on its fourth generation of partial reconfiguration technology and about to offer its fifth generation. The spokesperson denied that the technology has failed to gain traction. "We keep offering it because there's a demand for it," he said.

The customizable hard IP blocks that Altera will enable customers to use at 28-nm are embedded HardCopy blocks that customizable and utilize the capabilities of Altera's HardCopy ASICs, the company said. Altera's HardCopy ASIC technology.

Altera said it has also developed 28-Gbps embedded transceivers that will enable customers to implement next-generation designs such as 400G systems on a single chip without the need for external components.

Altera currently offers what it claims to be the fastest transceiver available on an FPGA. Stratix IV GT EP4S100G2 FPGAs offer an 11.3 Gbps transceiver.

"The market is just touching on 40G and looking at 100G, so 400G is pretty far out there," Wawrzyniak said. "But the way they've got this configured, you can split this up into many lower speed channels that are closer to what customers are looking with some really high-speed channels."

According to Altera, the rapid growth of bandwidth-intensive applications such as high-definition video, cloud computing, online data storage and mobile video has created a challenge for infrastructure and end-user equipment developers. The company said the innovations targeted for its 28-nm chips were developed to solve these challenges.

"I think they are exactly right on this bandwidth issue," Wawrzyniak said. "It is an issue and it's going to become a bigger issue as time goes on, especially as more and more people use devices that are going to tap into this bandwidth."

By: DocMemory
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