The architecture includes a high-speed switch to allow multiple DSPs to communicate and access memory resources. The architecture supports multiple DSPs operating at up to 1.2-GHz clock frequency and supports fixed- and floating-point processing within each DSP core. At that clock frequency the architecture can theoretically provide to 256-GMACS and 128-GFLOPS, TI said. The result, the company claimed, is the industry's highest performing CPU.

The company went further and claimed that the multicore SoCs could deliver five times the performance of existing solutions in the market and provide the main processing power for infrastructure products such as wireless basestations, media gateways and video infrastructure equipment.

TI is introducing a family of products based on the architecture starting with four-core device for wireless base stations and an eight-core device for media gateway and networking applications. However, TI did not say what manufacturing process technology it plans to implement the architecture and products in first. TI is providing application-specific software libraries and platform software to go with its hardware.

A 2-Tbit/s on-chip switch fabric called TeraNet 2 provides interconnection between all of the SoC elements, said TI.

"With this new multicore architecture, we challenged ourselves to exceed Moore's Law by bucking the trend of simply linearly increasing the amount of cores on each platform; instead, we increased overall performance with significant enhancements to the DSP, a new breed of coprocessors, and reduced power consumption," said Brian Glinsman, general manager of TI's communications infrastructure business.

TI says products from the new multicore portfolio will begin sampling in the second half of 2010.

By: DocMemory
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