Two other papers at the conference raise thermal and noise effects as potential reliability issues for phase-change memory.

The issue of current density is described by the researchers in the abstract for their paper — 5C4 in the program — as a potential "showstopper" to the scaling of PCM beyond the 32-nm manufacturing process node. The paper is due to be presented at 9:45am on Thursday May 6 and its contents may help to determine whether phase-change memory has a future as a mainstream semiconductor memory technology.

The abstract acknowledges that current density needed to program phase-change memory increases linearly with lithography reduction and will be of the order of 20-MA per square centimeter in the select transistor and 200-MA per square centimeter in the storage element at the 16-nm node.

"The aim of the paper is to investigate the impact of increasing current density on function and reliability down to the 16-nm node," the abstract states.

Paper 2C5, authored by a team from Stamford University and due to be presented on Tuesday May 4, looks at the impact of thermal cross-talk disturbance on the reliability of phase-change memory. The abstract states that the thermal disturbance can produce a 100 percent variation in threshold switching voltage. The authors propose a method to exploit thermal disturbance to improve the reliability of multi-bit per cell operation.

The abstract for paper 6C3, from researchers at Politecnico di Milano, deals with the so-called Telegraph noise effect, which it states has recently been observed in phase-change memories as a result of cell downscaling. The paper studies random telegraph noise in PCM in the frequency and time domains and discusses possible physical origins for the noise.

By: DocMemory
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