Given Altera Corp.’s earlier statements regarding 28-nm processes and HardCopy architectures, the capabilities of Stratix V were known long before the April 19 launch of the family. Still, the justification for the 28-Gbit/sec transceivers and 1.6-Tbit/sec aggregate switching capability aims for a core transport application space that may be only a partial realization of the inherent drivers for this FPGA. The nice thing about the physical-layer speed and the re-design of the adaptive logic module (ALM) is that it allows the Stratix V to be considered “wherever you have a wide datapath running at very high frequency,” said Paul Ekas, director of component and IP product planning at Altera.

Altera’s marketing foils don’t necessarily speak to the change in end designs that has taken place over the last few generations of FPGAs. The examples used of a multiport 100-Gbit Ethernet line card, and a multiservice Optical Transport Node muxponder, are certainly great examples of where the Stratix V would be an ideal ASSP replacement. The problem is, these large centralized transport nodes are now the sole province of three or four OEMs, including Cisco, Huawei, and Ericsson. For the most part, these companies are sticking with ASICs developed internally.

Where the Stratix V might find an immediate home is at the network edge, where smaller enterprise platforms perform stateful inspection and unified threat management. Five or ten years ago, such systems would have been limited to 100-Mbit or 1-Gbit links. Today, the demand for at-speed deep packet inspection has pushed performance requirements for network-edge devices to the level of core transport. And here’s where the Stratix V might have its best opportunity at obsoleting the ASIC.

Floating-point DSP parallelism is another realm where Stratix V may knock out any remaining standalone DSP processors, even those specific to floating-point applications. We’ve documented how FPGAs already are taking over the bulk of mil-aero COTS boards from vendors like Curtiss-Wright, Pentek, and GE Intelligent Solutions. Expect this to accelerate with the GS version of the new Stratix V (I should specify, the new family features the GT model, with 28-Gbit transceivers; the GX, with 600-Mbit to 12.5-Gbit transceivers; the GS version for DSP; and the E version, for very high density emulation and ASIC prototyping.)

Ekas said he sees very little design lag between Stratix IV and V, since some developers of 40- and 100-Gbit Ethernet can use the advanced capabilities today. That’s why Altera will support Stratix V design in its Quartus II design software by the end of this quarter, even though the first devices won’t be sampling until very early 2011. The company has to be ready to knock out the few remaining ASICs and DSP processors out there.

By: DocMemory
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