AMD will describe its new high-end Bulldozer and low-power Bobcat x86 cores at the event hosted at Stanford University. Bulldozer includes AMD's first multithreaded x86 engines that share resources such as branch prediction and fetching units in an out-of-order design capable of issuing four instructions per clock cycle.

This is a radical architecture change," said Jose Renau, co-chair of Hot Chips and an assistant professor for computer engineering at the University of California at Santa Cruz. "Since AMD has been in trouble these could be do-or-die chips for them," said Renau.

"In the same way the move from the AMD K5 to the K6 was a big change, so the move from the Opteron to the Bulldozer is a huge change," said Renau.

A paper on instruction set extensions to the ARM 7 is likely to be more significant than it looks from the title. The extensions include support for features targeting computer servers such as virtualization, enhanced security and possibly 64-bit addressing.

ARM and partners including Marvell have been working on an initiative to drive the ARM architecture into a new class of low-power servers for Web 2.0 applications in big data centers.

Separately, Microsoft will detail a new SoC that integrates as many as three chips used in previous versions of its Xbox 360 videogame console. The chip is believed to contain multiple PowerPC cores, AMD graphics cores and embedded DRAM. The chip powers a new version of the console announced last week.

Two other papers will give insights into China's growing silicon design sophistication.

The Chinese Academy of Sciences will detail the Godson 3c, a 16-core version of the China-grown processor based on the Mips64 instruction set. The new version, also known as the GS464V, includes 512-bit vector processing extensions and is made in 32nm technology.

"It's a big jump for them" compared to the previous four-core, 65nm version of Godson, said Renau.

"From what we saw in the abstract, they are aiming at video streaming and supercomputers because they are running benchmarks like Linpack and getting more than half a teraflop performance per chip with high energy efficiency for large scale systems," he said.

"I am envious they have so many students to develop a project like that," Renau added.

China's Dawning Computer recently designed the world's second fastest supercomputer using Intel Xeon and Nvidia graphics chips. Designers at Dawning said the company's next system will use the new Godson part.

In networking, China's Huawei Technologies will detail its work on a packet forwarding processor for routers that uses a novel memory technology.

"Huawei is becoming big in China, and competitive with Cisco Systems in some respects," said Renau. "This is one of the first times they are talking about something a couple years out," he said.

The conference includes a session on FPGAs in which Xilinx will further detail its work on a 28nm design that includes support for embedded ARM A9 hard cores. "This is a change for them because they didn’t have hard cores previously and they used PowerPC cores," said Renau.

The conference runs August 22-24, starting with tutorials on non-volatile memory and optical interconnects. "Very simple systems using on-chip optical interconnects could be ready for commercialization relatively soon," said Renau.

The interest in non-volatile memory comes from two areas. Phase-change memory and other non-volatile architectures could replace DRAMs which are slowing the rate of scaling at 22nm and lower. And flash drives are having a significant impact on server design, Renau said.

By: DocMemory
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