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Mobile applications push for breakthrough in packaging
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Thursday, August 26, 2010
We hear a lot these days about 3D integration and the many benefits that vertical scaling can bring with it. But there is a significant amount of semiconductor packaging innovation still taking place in the 2D arena as prominent consumer applications put more demands on chip size, performance, functionality, and cost. And ultimately, those 2D innovations will also lead to further enablement of 3D technologies.
As traditional CMOS scaling finally reaches its limits, the industry is looking at a variety of ways to continue on a path of functional scaling. This quest has brought about what Bill Bottoms has referred to as "an unprecedented pace of innovation in assembly and packaging technology."
Bottoms, who chairs the Assembly and Packaging Technical Working Group (TWG) for the International Technology Roadmap for Semiconductors (ITRS), and is also chairman and CEO of Third Millennium Test Solutions (3MTS), spoke recently about the benefits that deep submicron scaling brings such as higher performance, lower power, smaller chip sizes, and package-level systems integration, as well as the challenges that go along with trying to achieve so many things at once.
The move toward 32- and 28-nm technology nodes brings with it fragile low-k dielectric materials, physical stresses, thermal stability issues, and a host of other technical challenges that the packaging industry is addressing head on. Increasing demands are not only driving packaging technologies increasingly into the wafer-level domain, but are also creating a need for innovative ways to increase interconnect densities.
The mobile push
So why the drive to push past all these challenges? In short, the mobile market is extremely enticing. In the past, standard cell phone technology called for added functionality, decreased size, extended battery life, and lower cost. "Ultimately, the goal there was to get cell phones into as many people's hands as we possibly could in the industry," said Dave Stepniak, manager of wafer-level packaging at Texas Instruments (TI). "And the industry did a great job there; there's about 4.6 billion people today that use cell phones, and that's a good percentage of the world population."
But the market gets even more lucrative for chipmakers heading into the market for smart phones and other mobile devices with further increasing functionality. The silicon content in a smart phone could total more than $70, Stepniak said, compared with just a few dollars for a standard cell phone. "So it's a good market space for the semiconductor; it's very healthy for us, and it's a growing market," he said, adding that the smart phone market is expected to grow from approximately 250 million units to approximately 450 million units over the next couple years.
Besides increased memory capacity and bandwidth, the new consumer technologies require lower operating voltages to increase battery life, higher frequencies, and increased I/Os. In terms of die size, not only are x and y important, but also height. Devices are getting thinner and thinner, creating additional challenges with warpage on the package side.
"What we see as we move forward relative to the increasing frequencies is that the wire bond is running out of steam," Stepniak noted. "As you go above 1 GHz, you start to go to flip chip because of the parasitics that start to play within that package." Flip chip, however, is beginning to push the limits of I/O density, prompting designers to explore new packaging possibilities.
Approaches for denser interconnects
There's more than one way to skin a cat, and the industry is trying different approaches for increased densities and finer-pitch interconnects. Fan-out wafer-level technologies, for example, overcome interconnect density limitations on PCBs, and reduce the need for bump interconnects. Based on fan-out technology, Infineon's embedded wafer-level BGA (eWLB), produced in conjunction with STATS ChipPAC, STMicroelectronics, and ASE, is going into production this year at 200 and 300 mm. STATS has qualified a multi-die (SiP) eWLB process, and stacked eWLB processes are being developed.
Die embedding is another technique that has been going on for several years, with work from Casio, Imbera/Daeduck, Ibiden and AT&S, according to Venkatesh Sundaram, director of research at Georgia Tech's Packaging Research Center. The benefits of fan-out and die embedding technologies are obvious, Sundaram said. "With these technologies, you can really shrink your interconnect pitch much finer. So rather than a flip chip of 150 micron today, fan-out already is at 80-micron pitch," he said. "And of course lower profile because you don't have much of an interconnect to deal with between the chip and the substrate, and the same goes for electrical."
Although chip-first embedding enables very high-density first-level interconnections, it does create concerns about manufacturability and yield, especially for multilayer and complex modules, Sundaram said. "There's testability and yield concerns because you can't test anything until you finish your package," he explained. "So if you have five dies in your module, you have to commit all your dies and test at the very end." The business model is also complex, he added, with concerns about who will take ownership of the packaging - substrate supplier, assembly supplier, or semiconductor manufacturer.
Georgia Tech, therefore, began to look for an alternate solution, and came up with chip-last embedding, which enables intermediate testability. "If you have five dies, and one of them is really high value, you could test the package with the other four dies embedded, and then you could commit the really expensive die," Sundaram explained. "So really it gives you some flexibility in dealing with the yield issue of committing the chips." Selective site embedding also means that it's not necessary to have dies in every site, unlike chip first, which requires a die in every site before building the wires.
The interconnection, which is similar to flip chip, accommodate multiple I/O pads, enabling mix and match with various metallizations. "We are now working on what we call ultra-short microbumps, but we are also trying to go into bumpless connections so you don't have to actually bump the wafers before you commit them to this embedding," Sundaram said.
Fine-pitch copper pillars
TI and Amkor Technology Inc announced last month an entirely different approach that uses fine-pitch copper pillars on flip-chip packages and a new assembly process to enable I/O pitches to shrink from 150 micron to 50 micron (and anywhere in between). Although copper pillars have been explored previously (Intel announced its use of copper pillars in 2006), the new jointly developed process takes copper into the fine-pitch realm for the first time. "We believe this is an industry game changer from a technology standpoint, a significant advancement in flip-chip technology," said Mark Gerber, manager of TI's worldwide copper pillar program.
Besides the finer pitch, which enables higher-density I/Os for increased functionality and smaller die sizes, Gerber also noted the technology's benefits in terms of low-cost manufacturing and the lead-free solution.
Although the technology could be useful for a number of applications, it is particularly suited to applications processors, Gerber said. In this space, "there's a drive for reduced body size - the x-y on the overall packaged chip solution," he said. "There's also a requirement for the package solution being very thin. Generally, these types of devices have high pin counts - greater than 300 I/O. And with those specific requirements, this device space is one that the fine-pitch copper pillar technology can really help to enable a long-term roadmap." Digital signal processors have some similar requirements, he noted, as do power management solutions. Although power management devices may not have quite as high pin counts, smaller die sizes mean that bump density is still a challenge.
Enabling 3D integration
According to a recent wafer-level packaging report from Yole Développement, fan-out wafer-level packaging and chip embedding are both technologies that could expand the capabilities for 3D packaging, since they "enable the construction of ever more complex, larger SiP modules with different active and passive functions, all connected on both sides of the active substrate."
TI contends that its fine-pitch copper pillar technology also is well suited for the next generation of packaging technologies, including the integration of through-silicon vias for 3D integration. "Looking at those next-generation needs, trying to tie everything together of how to make sure you've got a long-term solution and not one that's just a point solution," Gerber said.
By: DocMemory
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