In an exclusive article in Microprocessor Report this week, Broadcom revealed that it has developed a new MIPS-compatible CPU, the BRCM 5000, for its broadband SoCs. This CPU, also known by its code-name Zephyr, is the latest in a series that the company has developed over the past decade under an architecture license from MIPS.

According to Dan Marotta, executive VP and general manager of Broadcom's Broadband Communication Group, these CPUs have been a secret weapon for the company. "Our small but powerful CPU cores enhance the capabilities of our industry-leading digital-home solutions," Marotta said. "As a result, Broadcom processors enable a better consumer experience than products based on commodity off-the-shelf cores." Products using these Broadcom-designed CPUs generate more than $2 billion per year in sales.

The BRCM 5000 is a superscalar CPU that can execute two threads at once. The design is now entering production in 40nm G technology at a clock speed of 1.3GHz. With a rating of 3,000 Dhrystone MIPS, the CPU provides plenty of performance for high-end set-top boxes (STB), digital TVs (DTV), DOCSIS 3 cable modems, and other demanding consumer applications. It appears in products such as the BCM7420.

Broadcom's CPU development stretches back more than 10 years, when the company shipped its first DSL chip with an internally designed CPU, now known as the BRCM 3300 core. This CPU, which the company still uses today, is quite small (less than 1mm2 in 40nm CMOS, including cache), making it ideal for low-cost products such as ADSL chips. The simple scalar CPU uses a six-stage pipeline to achieve clock speeds of 700MHz in 40nm G, as Figure 1 shows. It generally uses 32KB of instruction cache and 16KB of data cache, although the synthesizable design can be configured in multiple ways. The small data cache is optimized for broadband applications, in which most of the data is streamed through the processor and doesn't need to be cached.

Broadcom later developed the BRCM 4355 CPU for higher-performance modems (e.g., VDSL) and set-top boxes. This design is a dual-CPU module in which the two CPUs share a single data cache. This structure was originally designed to simultaneously support two operating systems—for example, a real-time OS (RTOS) to process broadband data and Linux to provide a user interface. The shared 32KB data cache simplifies synchronization and avoids wasting cache on streaming broadband data. Each of the two CPUs is similar to the BRCM 3300 in speed and issue rate.

A more recent version of this CPU, called the BRCM 4380, expands the shared data cache to 64KB and adds an exclusive 128KB level-two cache. This design also adds DSP extensions and a floating-point unit to accelerate 3D user interfaces in set-top boxes. This CPU, which achieves a speed of 700MHz in 40nm G, appears in Broadcom products such as the BCM7400, BCM7405, and BCM7335 STB processors.

The company started a parallel CPU effort in 2000 when it acquired SiByte, a startup that had developed its own high-end MIPS CPU. In 2005, however, Broadcom decided that integrated SoCs were a better investment than standalone processors, so it merged the SiByte CPU team with its in-house efforts. The new team brought extensive expertise in high-performance CPU design, allowing Broadcom to develop a much more powerful CPU: the BRCM 5000.

By: DocMemory
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