|
 |
|
|
|
Suvolta promise 20nM geometry and 0.5V power
|
Thursday, June 23, 2011
SuVolta, a startup process IP company with deep roots in device design and modeling, has developed a new transistor that could challenge finFETs and SoI at 20 nm and below, as the conventional planar MOSFET begins to run out of steam. Built in a conventional process but offering channel mobility approaching that of intrinsic silicon, the PowerShrink technology raises the prospect of power savings on the order of a factor of five, lower operating voltages, vastly reduced threshold variations, and more to come.
The key to the technology, according to SuVolta CTO Scott Thompson, is that the transistor is in every way like any other planar MOSFET-with one huge difference. The PowerShrink device has a shallow, updoped channel that operates in deeply depleted mode. In this sense, the device is more like a fully depleted SoI (FDSoI) MOSFET. But the SoI device requires a special FDSoI wafer that has only a 10- to 15-nm layer of silicon over a buried layer of oxide.
In contrast, SuVolta's device creates the same ultra-thin 5-nm-thick channel by implanting few-atoms-thick dopant layers beneath the channel. These implants apparently form a buried junction that, when properly biased, depletes the thin active region of the channel almost completely. The result is a device that exhibits the very low leakage, very high mobility, and very low threshold variation of FDSoI, but on a conventional wafer and process.
Working with licensee Fujitsu, SuVolta has begun to demonstrate results at the chip level. Fujitsu has fabricated a 200 million-transistor, 65-nm SRAM using the PowerShrink transistor in the digital nets, SRAM cells, and sense amps, and conventional transistors for the analog and I/O circuits. Thompson said the device can operate 300mV below the operating voltage of a comparable conventional SRAM, it consumes half the dynamic power and shows as little as a fifth the leakage. SuVolta has also demonstrated devices at 28 nm with an unidentified foundry partner.
The new transistor requires no new mask steps, Thompson said: just a change in the order in which the masks are used. The process can use existing layouts, although SVolta may synthesize a new implant mask using their own mask generator and checker algorithms. You can use your existing strain-engineering structures, as well. In fact Thompson pointed out that the impact of strain on channel mobility should be greater because of the very low impurity concentrations in the channel and the quite large channel volume, compared to a fin.
Moving forward, Fujitsu has announced plans to use the technology commercially in its internally designed ICs, its ASICs, and its foundry offerings at 65 nm. SuVolta is seeking additional licensees, as well. And the company has some additional tricks up its collective sleeve.
Thompson said that by applying a bias voltage to the buried layers, you can dynamically control the threshold voltage on individual transistors. Exploiting this capability requires circuit-design changes, and consequently SuVolta intends to license circuit, as well as process, IP. "We believe this technology makes 0.5V operation feasible," Thompson said. "It extends the life of the planar transistor past 20 nm."
By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved
|
|
|
|
