Thursday, July 14, 2011
Samsung Electronics has taped out an ARM processor test-chip intended for manufacture in a 20-nm process with high-K metal-gate technology.
Samsung worked with IP licensor ARM Holdings plc (Cambridge, England) and EDA companies Cadence Design Systems Inc. and Synopsys Inc. to complete the design.
At 20-nm a different approach to chip design is required compared with what has been used in the past, Samsung said. The company said its 20-nm process includes new device structures, local interconnects, and advanced routing rules. The company is switching to gate-last HKMG at 20-nm having used gate-first HKMG in its two previous HKMG generations at 32- and 28-nm.
ARM physical IP and processor IP are deployed in the test chip and Samsung said it used both the Cadence unified digital design flow and the Synopsys Galaxy design flow to implement different components and check out that both the Cadence and Synopsys design flows would work.
ARM did much of the design work which contained a Cortex M0 processor, custom memories, general purpose I/O and a number of discrete test structures.
By: DocMemory
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