Globalfoundries has announced that it successfully taped out a 20nm test chip using flows from EDA partners Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys. The foundry said it is ready for customers to begin evaluating their 20nm designs.

All four EDA companies have demonstrated that their place-and-route (P&R) tools and tech files are capable of supporting the advanced rules associated with the 20nm process, Globalfoundries indicated. The flows include library preparation steps for double patterning technology. The 20nm test chip requires double patterning and was implemented with each EDA partner contributing a large placed and routed design.

In addition to demonstrating full support for all of the key steps in a 20nm P&R flow - including double patterning library preparation, placement, clock tree synthesis, hold fixing, routing and post route optimization - Globalfoundries worked with each of the EDA suppliers to include the necessary setup and support for technology and mapping files. The flow will also demonstrate foundry support for extraction, static timing analysis and physical verification.

Globalfoundries said it will make the design, libraries, and complete vendor flow scripts available to customers who wish to evaluate 20nm technology.

By: DocMemory
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