Monday, December 19, 2011
JEDEC which announced a broad set of 3D IC standards development earlier in 2011 is all set to release what is touted as the first 3D IC interface standard which will be out in late December of this year (or some time in January 2012).
At GSA's 3D IC task group meeting held earlier this week, Intel's Ken Shoemaker presented more details of the WideIO Memories where more details of the electrical and mechanical interface were shared.
JEDEC has a head start in releasing 3D IC standards –its standard for reliability of 3D chip stack with through-silicon-via (TSV), JEP158, was released in Nov 2009 . With the soon to be released WideIO standard, it appears it is maintaining that lead, for now among the standards generation efforts of SEMI, Sematech and Si2.
The industry consensus is that LPDDR2 will run out of bandwidth before WideIO memories are commercially available. LPDDR3 (which is a linear evolution of LPDDR2) is expected to fill this gap by supporting higher operating frequencies while maintaining power efficiencies of LPDDR2. The 800MHz LPDDR3 will feature 50% more bandwidth than a 533MHz LPDRR2 while retaining the equivalent pin count as LPDRR2.
 Figure 1. WideIO Positioning Source: Sophie Dumas, ST-Ericsson, Mobile Memory Forum, June 2011;
Developed by JEDEC task group JC42.6 which began its work in December 2008, WideIO is explicitly a 3D standard for now (2.5D interface is on the future development roadmap) combining logic and DRAM in the same package to reduce interconnect capacitance. The soon-to-be released specification calls for a maximum 4-dice stack of memory cube that can interface to a logic SoC with a maximum target package size of 10x10x1mm.
JC42.6 for WideIO specifies the logic to memory interface (LMI) leveraging the work of two JEDEC committees –JC42.6 (Low Power DRAMs) and JC11 which has a long-standing in mechanical standardization of chip packages. The mechanical interface between memory logic and memory has been generically named as Micro Pillar Gate Array (MPGA, link).
The interconnect method between logic and memory is not specified and can be micro bumps, micro pillars, etc. The standard also specifies boundary scan to test interconnect continuity, post-assembly direct-access memory test, location of thermal sensors in the memory dice, and the exact mechanical layout of the chip-to-chip interface.
The standard does not specify the memory-to-logic interconnect design or method of assembly. The exact location of the interconnect on either the memory or the logic chip is not specified as are the dimensions and locations of TSVs. The thickness of memory and logic chips, assembly methods and post-assembly test methods are all unspecified.
By: DocMemory
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