Korean memory maker Hynix recently introduced its 30-nm class (3X) DRAM. UBM TechInsights performed a complete structural analysis of the low power, 2-Gbit DDR3 SDRAM H5TC2G83CFR-H9R.

Surprisingly, the wordline (WL) pitch measured in the bitline (BL) direction was found to be the same as in the previous generation Hynix 44-nm 2-Gbit DDR3 SDRAM, which was measured to be 88 nm. Usually, the technology node for DRAM is defined as the half-wordline pitch. According to the standard definition, the H5TC2G83CFR-H9R device remains at the same node as the previous generation. However, the unit cell of this new device is 40 percent smaller than that of the 44-nm node device.

As seen in the figure below, the process integration scheme is significantly different: The Hynix 44-nm SDRAM has a WL above the Si substrate level and the array transistor employs the saddle-fin structure; the new Hynix SDRAM has a WL below the substrate surface and uses the buried-wordline (bWL) scheme.

Figure 1: Unit cell and wordline (WL) pitch, SEM cross-section, in bitline direction. Hynix 44 nm and Hynix 31 nm both have the same WL pitch (88 nm), which by conventional definition implies that the technology node is 44 nm. Hynix 31-nm device uses a buried wordline line integration scheme and has a smaller unit cell than Hynix 44 nm.

Pitch defines node

Another common definition for technology node is the minimum lithographically implemented feature size. In the early nodes, as seen in the table below, the shallow trench isolation (STI) pitch, BL pitch, and the WL pitch are all similar. Half of the WL pitch represents the minimum feature size. After the 70-nm node, the STI pitch shrink did not keep pace with the WL pitch shrink until the recessed-channel-array-transistor (RCAT) was introduced by Samsung and later by others. RCAT shrunk the STI pitch in the array. When Samsung introduced its 30-nm class SDRAM K4B2G0846D 2Gbit DDR3, it used STI pitch to define process node.
 
The Hynix 30-nm-class SDRAM followed the same trend. Micron is the only major SDRAM manufacturer that still uses the historic definition of half WL pitch to define the technology node. Micron’s 30-nm class SDRAM MT41K512M8RH-125 has a half WL pitch of 31 nm and half STI pitch of 45 nm. Irrespective of what parameter the manufacturer has taken as the minimum feature size, one parameter is common: every new technology node has a smaller SDRAM cell area than the previous generation.

Table 1: Summary of 6 generations of Hynix SDRAM products.
(*STI pitch is measured perpendicular to the active array and its half pitch is used to define the technology node for Hynix’s 30-nm class SDRAM)

1.The noise immunity is higher and the process complexity is lower due to larger cell size compared to the 6F2 layout.

2. Conversely the 6F2 scheme provides a significant (25 percent) cell area reduction with the same design rule. Micron was the first company to switch to 6F2 with its 95-nm node SDRAM and Samsung introduced 6F2 layout in its 80-nm node SDRAM. Hynix continued using 8F2 layout until the introduction of this device.

Saddle-fin transistor

At the 44-nm node, Hynix used a saddle-fin transistor as an access device but maintained the old layout of 8F2. The saddle fin scheme is essentially a combination of FinFet and RCAT process-flows. The saddle-fin transistor was designed to decrease storage node write time as well as improve short channel effects with the addition of a partial triple-gate structure. The result is better control over the channel region than the RCAT structure used in Hynix 54-nm SDRAM.

However, it has become increasingly difficult to shrink the cell size using the 8F2 layout. As a result, Hynix eventually adopted the 6F2 layout while also implementing the bWL concept. In the bWL cell, the transistor gates are merged with the metal WL running below the silicon surface level, thus enabling a simple cell structure. Due to a less complex structure, the BL-to-WL capacitive coupling is strongly reduced, resulting in a higher read margin and, subsequently, lower power consumption.
The die is fabricated using a 3x nm CMOS process with stacked capacitor and bWL scheme. Hynix has kept the same WL pitch as that of its previous generation but has reduced the STI spacing by making the active area slanted by 19 degrees from the BL direction as shown in the figure below. The slanted active areas are not continuous but form islands separated by STI. The 6F2 SDRAM unit cell measures 0.131 µm and 0.071 µm along the WL and the BL directions respectively, resulting in a given unit cell area of 0.0093 µm2.

Figure 2: SDRAM array, at diffusion level, SEM topographical view of Hynix 44 nm (left) and Hynix 31 nm (right). Active areas of Hynix 31-nm device are slanted and the bitline makes a 19 degree angle with the active area.

Storage-node contacts

Each slanted active area has two storage-node contacts (SNC) and one BL-contact. For slanted active areas, SNCs and BL-contacts are automatically staggered in the BL direction, which implies that in any given BL direction either a row of SNC exists or a row of BL-contacts is found – but not both (as shown in the figure below). This configuration helps to reduce the cell area and to keep straight bitlines.

Figure 3: SEM cross-sections through storage node contacts and bitline contacts, Bitline direction for SK- Hynix 31 nm SDRAM. The SNC and the BL-contacts are staggered along BL direction due to the slanted active area.

The rest of the Hynix 31-nm device process is similar to its previous 44-nm node technology.
 
Even though the capacitor module and the peripheral transistors are identical to the previous generation, the 30-nm-class Hynix SDRAM is still a major step for the company and its viability. Hynix had put considerable R&D effort into saddle-fin technology but has used it once before – for the previous technology node (44 nm). This is not cost effective in terms of production.

Smaller cell area

Moreover, Hynix has also switched over to a 6F2 layout from a 8F2 layout, which it used for at least five generations. In a commodity market with ever-diminishing profits, it is necessary to critically analyze one’s own cherished technology and evaluate if it can be prolonged or adapted to future technologies. Hynix has survived and adoption of the bWL and the new 6F2 layout has given the Hynix 31-nm device a smaller cell area comparable to that of other two major SDRAM manufacturers (Samsung and Micron).

The figure below shows the square root of DRAM cell area versus technology node. For earlier generations, by the given design rule, the cell area of Hynix’s SDRAM device is larger than that of Micron or Samsung. That is because the other two manufacturers chose to utilize the 6F2 layout. This same figure also suggests that for each manufacturer the square root of its SDRAM cell area decreases linearly as a function of technology node.

For future technology nodes, it may be difficult to compare the effect of device geometry scaling and cell array-architecture change, as device makers are trying different ways to reduce the cell area and increase the Mbytes/ cm2. It makes a lot of sense to consider the SDRAM unit cell area as the main parameter to define a technology node.

 
Figure 4: Square root of unit cell Vs technology node for three major DRAM manufacturers.

UBM Techinsights analyzed recently the 30-nm class SDRAM of Samsung, Hynix, Micron and Elpida. All four manufacturers use different novel process innovations to shrink their respective SDRAM cell area.  From this analysis, it is interesting to see the novel approach each DRAM manufacturer takes in developing towards their next process shrink as the highly volatile and competitive DRAM market is taken into consideration with each design.

By: DocMemory
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