Both Toshiba Corp. and Taiwan Semiconductor Manufacturing Co. Ltd. have developed mask read-only memories (MROMs) that can offer greater data density by storing multiple bits per cell.

Conventionally mask ROM is formed by the cross-point of single word and bit lines and stores a single-bit per cell depending on whether a diode links them or not. However, due to the variability of fabrication at advanced manufacturing nodes and the narrowing of the channel area of the cell transistors, at the 40-nm node access time increased compared with the previous process generation.

Toshiba has developed a multi-bit cell that uses twice the area of a standard single-level cell and reported on this at the 2013 Symposium on VLSI Circuits, held in Kyoto, Japan, last week.

The paper proposes a triple-wire program cell (TWPC) that consists of a single-transistor with triple bit lines and storing two-bits of data per cell. Toshiba has built the memory in 40-nm, 1-Mbit test chips and said that the access time is improved by 38 percent using TWPC. The power consumption in both active and standby modes is at the same level as the conventional case.  The scheme also triples the current characteristic of the cell without any change in the memory capacity per area. It reduces the influence of the variation in fabrication by 42 percent, Toshiba said.

MROM's main role is to store the boot loader or firmware that can then load other software from non-volatille memory when equipment is switched on. However, the amount of MROM required for system-on-chip applications is increasing for applications such as smartphones and tablet computers.

Toshiba said it aims to ship SoC for digital applications that implement the multi-bit MROM cell in 2014.

However in the paper that followed Toshiba's, foundry chip supplier TSMC announced it had created a twin-bit ROM cell in 28-nm process. The paper covered a two-step decoding circuit that is suitable for either single-ended or differential sensing. TSMC reported that their scheme improves access time by 30 percent and reduced supply voltage Vcc minimum by 190-mV in TSMC's 29-nm low-power process.

By: Docmemory
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