Increasing the density in conventional flash memory is hitting a lithography roadblock. As a result, memory vendors are looking to build up (as in layered or vertical/3D flash) to satisfy the demand for mass storage. The challenge is, when you layer, all the processing steps change.

That's where Imec, the nanoelectronics research group, comes in. Headquartered in Leuven with a staff of more than 2,000, it performs leading-edge research in nanoelectronics, and it recently announced a new approach to vertical memory.

Imec began working on vertical flash about five years ago. It saw there would be a major lithography problem as flash became more complex, so it started looking at layered flash. One of the main challenges with this approach is that the channel material (which conducts the current of the memory transistor) is of a very low quality, because it is defined in polycrystalline silicon. One way to improve this quality post-processing is to anneal it and hope it recrystallizes. But Jan Van Houdt, director of flash memory at Imec, told us this approach yielded only marginal improvements. "So then we came up with the idea for laser annealing."

In this technique, a laser is used for very local melting of the polysilicon material, which can make more monocrystalline materials. The melting occurs at the top of the wafer. When the laser is removed, the heat travels down the channel and continues the recrystallization.

The Imec team decided to work with Excico, a French startup with a system that seemed suited for this type of application. Imec said in a press release that the pulsed laser annealing uses an Excico LTA series laser with a wavelength of 308 nm and a pulse duration of less than 200 ns. Imec sent the devices to Excico, which did the laser annealing and returned them for final electrical work. "The current in the channel increased substantially," Van Houdt said.

Specifically, Imec reports that, with the larger grain size of the laser-recrystallized polycrystalline channel material, the application delivered up to 10 times higher read current and 2.5 times steeper sub-threshold slope over a conventional polysilicon channel in a vertical device.

Van Houdt said that, in order to stack layers in memory chips, you need to increase the read current. For example, if you can get 2X more current, you can double the layer on the chip for exactly the same dimensions. Working with the major memory suppliers -- Intel, Micron, Samsung, SK Hynix, GlobalFoundries, Panasonic, Toshiba, and SanDisk -- Imec has made major improvements in current (Ion) and leakage current (Ioff).

The first application for the Imec technology is 3D memory, but in principle, it could also be used for logic and DRAM. "This creates an entirely new roadmap where a vertical device is made with one lithography step, and it is now about how many layers you can stack," Van Houdt said. "The search for better channel material is really the holy grail in this technology."

Are there alternatives to laser annealing? Another way would be to use a different material altogether in the channels, because the channel is no longer linked to the substrate material. However, according to Van Houdt, this is still quite a ways off.

In August, at the Flash Memory Summit, Samsung announced that it was going to production with the first version of a vertical device. Samsung claimed its technology can deliver 24 layers of stacked devices on the same chip.

Of course, the memory makers partnering with Imec are very interested in this new technology, but none of them are talking yet about how they plan to implement 3D memory. In the meantime, Imec remains focused on finding the optimal solution based on each memory architecture. It has also developed its own tools to quantify channel quality, so architectures and materials can be benchmarked against one another.

By: DocMemory
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