The semiconductor industry is at a deadlock over the next big thing: 3D chip stacks. Someone needs to blink before the technology will be viable for creating the next generation of high-performance, low-power systems.

It might be Globalfoundries undercutting rival TSMC on foundry prices for a 2.5D process-if it can deliver it. It might be Samsung trying to widen its edge on Apple in smartphone and tablets. Or perhaps Nvidia will take a big hit on margins (maybe even a loss) to grab a big chunk of GPU marketshare and mindshare from rival Advanced Micro Devices.

That was the picture from a panel discussion where a member of the audience made a shocking disclosure the Apple A7 SoC in the iPhone 5s is "a poor man's 3D IC."

Xilinx talked about how it is already shipping 2.5D stacks where die are laid side-by-side on a silicon interposer. So far it has discussed products using multiple FPGAs or an FPGA and serdes on a chip.

The FPGA vendor will describe at the International Solid State Circuits Conference in February a product that puts two 65nm serdes next to an FPGA. It is also said to be working on devices with an ADC and DAC next to an FPGA for use in cellular base stations. So the applications for these relatively high-cost, low-volume products are slowly expanding.

But so far the Xilinx products are consuming less than 200 wafers a month, according to estimates. So what's the path to high volumes of tens or hundreds of thousands of wafers per month? In a word, torturous.

TSMC claims it's a one-stop shop for 2.5D stacks, and Globalfoundries is at some stage of bringing up its own service. Having one neck to choke for a complex technology like 2.5D chips is great, but the foundries are charging a 10x premium. Yikes!

Graphics chip vendors such as AMD and Nvidia would love to put a nice big 3D memory stack on a silicon interposer next to their honking GPUs. The resulting products would have significantly higher performance and lower power, but not enough to justify the 10x manufacturing premium the foundries are charging.

So the industry is at a chicken-and-egg stand still for high volume 2.5D products.

Micron hopes its Hybrid Memory Cube could be the break out product. But it's not clear its high-end customers are the right vehicle. Fujitsu said it will show a prototype board at next week's supercomputer conference using (it is believed) as many as eight of the HMC stacks.

So the technology is real and has users, but not high-volume ones-yet. SK Hynix will show its own version of a memory stack that like Micron's has four to eight DRAM die delivering something on the order of 160 MB/second, so there is competition.

Potential customers say neither 3D memory company is ready to supply high volumes yet. Perhaps they will next year. They are also expected to roll versions that support the Jedec HBM interface for graphics processors. The question, again, comes down to price.

At the panel session, Abe Yee, a packaging expert at Nvidia, had some suggestions for the likes of Globalfoundries, Micron, SK Hynix, and TSMC.

"We've invested $2 billion in [the chip stacking] market already and haven't got it back, but we continue to invest—and our suppliers need to think the same way," Yee said.

"I don't think Moore's Law is going to last another 20 years, and even if it does we will still need to get memory closer to processors," Yee added. "So this market is going to happen if you like it or not, and suppliers have to think about how they will invest in it," he said.

Of course it's always easier to tell the other guy to invest the next billion. Meanwhile, the other billion dollar question is, what will Samsung do?"

The Korean giant has all the pieces—DRAM, flash, processors, and fabs. It has been selling as merchant products for some time 4GB memory stacks, so it has some 3D capabilities.

At ARM Tech Con last week, Samsung even teased attendees with a demo of a 3D stack of memory and its Exynos application processor using a Jedec Wide IO interface. It delivered significantly lower power than a traditional separate smartphone SoC and memory. But Samsung would not comment on if or when it would become a product.

There are a few problems with the "true" 3D stacks using through silicon vias to connect logic and memory for uses like smartphone SoCs. No one knows how to cool the logic, for instance, and the EDA tools and skills to lay out the TSVs are said to be immature.

In any case, Samsung's engineers likely have a good idea when it is economical to make a 3D IC for smartphones. Given it is already pulling ahead of Apple in mobile device volumes, the pressure may be off for the moment to jump to a new and risky technology.

Meanwhile, a veteran engineer in the audience at the panel surprised everyone when he chimed in with a data point. He had done a teardown of the Apple A7 processor in the iPhone 5S. It uses a very, very simple six layer board-two layers each for signal, ground and signal, he said. The memory is essentially on the other side of the simple board.

His analysis suggests Apple has discovered a low cost path to 3D ICs. Put most of the smarts in the SoC and use a simple pc board as "a poor man's 3D IC."

Perhaps the next iPhone will use an even simpler layer between its SoC and memory chip such as a flex circuit or a glass or organic interposer. It's a great way for a fabless company to compete with vertically integrated giant like Samsung.

So everyone is watching a few things very closely. What will Apple and Samsung do in mobile. And what will TSMC vs. Globalfoundries and Micron vs. SK Hynix do in 2.5D pricing.

By: DocMemory
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