Is Samsung Electronics (005930KS) about to upset the NAND chip party for Micron Technology (MU) and SanDisk (SNDK)? That’s a question pondered today by Cowen & Co.‘s Timothy Arcuri, who hosted a panel discussion on Tuesday about the emerging memory chip standard known as “3-D NAND.” The panel featured Applied Materials‘s (AMAT) Bradley Howard, head of “etch” tools, within its advanced technologies division; and a consultant form MKW named Mark Webb.

In contrast to a note last week from Piper Jaffray‘s Jagadish Iyer last week, claiming that 3-D NAND will be a while in coming, Arcuri points out that Samsung is making progress in producing the parts, which may spur Sandisk and Micron to become more aggressive with their own timelines:

Panelists felt p-BiCS (Toshiba/SNDK) will be “easier” to ramp, but TCAT (Samsung) will ultimately have more runway on both costs and transistor performance. On supply, the panel felt that likely <5% of Samsung ’14 bits would be 3D (i.e. ~1-2% incremental to global supply) but we continue to model 3D at ~10% of Samsung overall bits in ’14(~4% incremental globally), heavily skewed to late 2014. Ultimately, the panel agreed that if Samsung is even remotely close to achieving stated performance/timing , it creates multi-year technology risk for laggards, most specifically SNDK. Our checks indicate others like Hynix and MU (and even potentially Toshiba/SNDK) are starting to pull-in or at least strongly considering a pull-in of 3D NAND timelines.

At the same time, Arcuri concedes that there are a number of ways to extend the useful life of todays 2-D NAND technology for years to come:

Panelists presented data/models suggesting annual cost reduction for existing 2D planar is slowing from historical 40% Y/Y to 30% for 19nm and ultimately 15% for 16-18nm with little to no cost reduction beyond 15-16nm. 3D-NAND promises to ultimately bring the cost curve back at least in-line – and likely better – than historic 40% Y/Y cost downs. Timing-wise, 3D must achieve at least 32 layer (2nd gen) as 1st gen (24 layer) costs will still materially lag 16nm planar w/HKMG; thus, cost crossover would likely be mid to late 2015. Lithography scaling beyond the initial ~40nm range will be limited to only another ~15-20% given inherent challenges in shrinking charge-trap transistors. Thus, vertical scaling (good for AMAT/LRCX) will continue to drive cost down and is sustainable for another 8-10yrs. Ultimately, 96 and even 128 layer devices are feasible and even likely (Hynix recently showed a 100 layer prototype) but further improvements in equipment (deposition and etch in particular) throughput must occur to make it economically feasible. While some producers are discussing alternate longer-term technologies like ReRAM and MRAM, the panel felt these will likely remain niche technologies due to cost considerations.

Another individual reflecting on the technology today is Srini Sundararajan of Summit Research, who writes that clients have been asking him how much money the tools makers might make off of 3-D NAND production, especiall for tools used in metrology and “inspection.”

He points out KLA Tencor (KLAC) is one to watch, as it sells more than half of all metrology and inspection tools used in industry: “Our top-down estimates suggest that around $1B of added revenue may accrue to KLAC from 3D NAND on what we think would be KLAC’s revenues of ~ $14B over four (4) years. Not bad!”

If EUV is available earlier by lucky happenstance then planar NAND might survive up to 10nm. Furthermore, 2017 is pretty close to the timeline when all the memory players are hoping to have a non-volatile or an enhanced hybrid memory solution; we have not accounted for that either.

By: DocMemory
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