Wednesday, March 5, 2014
A UK startup has developed an entirely new way of building static memory on a standard logic process that cuts the power in half without paying a penalty in area or speed.
"Fundamentally memory has some real problems everyone does it the same way," said Mark de Souza, chief executive at Silicon Basis in Bristol and formerly at the memory IP supplier Virage Logic. "They all take the TSMC arrays and put them together."
Silicon Basis sees two key advantages for its technology: It can save up to 50% of the power consumption, and it can go below the bit cell voltage of the foundry memories. This allows the memories to be powered by the same voltage source as the logic and so eliminates the need for a second DC-DC converter. It also makes the technology foundry independent and scalable to new technologies such as FinFet, says de Souza. The company, based in the SETsquared center in Brunel's EngineShed in Bristol, has produced all the models needed and is now working on 28nm silicon to prove the implementation.
All this comes from a new way of looking at the design of the cell, which is currently being patented.
The technology has been characterized on the TSMC 40nm node and outperforms the high-speed bit cell, and also fully compatible with FinFet vertical structures being used in TSMCs 16nm process node.
By: DocMemory
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