Xilinx’s DDR4 memory interface for UltraScale devices has completed the Agilent Technologies N6462A compliance test running at 2400Mbit/s.

As defined by the JEDEC JESD79-4 DDR4 DRAM specification, the N6462A compliance test provides electrical and timing analysis for characterisation and margin testing purposes.

The DDR4 memory interface provides more than 1Tbit/s of memory bandwidth to handle the data flow demands of applications such as video imaging and high-performance computing.

Agilent’s DDR4 BGA interposers are designed to allow users to gain access to the DDR4 signals that are critical to DDR4 debug and validation. The interposers work in existing designs and eliminate the need for up-front planning or re-design by providing probe points that enable designers to see the actual clock and data signals using an oscilloscope.

“Together with Agilent, we have given customers the ability to accelerate the development of high-performance memory designs,” said Dave Myron, senior director of FPGA product management at Xilinx.

“We are shipping UltraScale FPGAs today that offer the industry’s first DDR4 memory solution and successfully meet the rigorous JEDEC standard as demonstrated via Agilent’s test solution.”

By: DocMemory
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