Synopsys, Inc. has unveiled a comprehensive LPDDR4 IP solution that boasts a speed performance of 3200Mbit/s for high-end smartphones and tablets. The solution includes the DesignWare LPDDR4 multi-PHY, Enhanced Universal DDR Memory Controller (uMCTL2) and verification IP (VIP), in addition to hardening and signal integrity services.

The solution includes a fast frequency switching, which levels the memory bandwidth with the device workload to optimise performance and power consumption. It also integrates multiple power-saving features—such as low-power modes, clock gating and power down of free sections in the PHY—to further reduce power consumption per bit transferred. These work to the advantage of thin and light devices that require extended battery life.

The solution is backward compatible with LPDDR3 and DDR3/4 SDRAMs, simplifying the design transition across SDRAM standards. It supports a split PHY implementation to allow IP distribution around the SoC for area-efficient PoP assembly.

Finally, the DDR hardening and signal integrity services ease IP integration and reduce potential risks in the use of advanced manufacturing technologies through multi-PHY hardening and signal integrity analysis.

The uMCTL2 is available while the multi-PHY IP and VIP are due later in the year.

By: DocMemory
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