Rambus will join Jedec Committee 40, which works on server and cloud memory standards. In February 2013, the company demonstrated a 6.4 GHz DRAM interface -- twice the clock rate of today's DDR4 chips.

Sources say there's nothing in the pipeline after DDR4, which is shipping in the latest DRAMs. For years, engineers have worked on 3D stacks of logic and memory, many using Jedec's Wide I/O interface standards, an area where Rambus also has expertise.

"In my opinion, what we should be investing in is both Wide I/O and DDR-like signaling," Kevin Donnelly, general manager of Rambus's memory and interface division, told press.

It's time for Jedec to start discussing DDR techniques like those used in the Rambus 6.4 GHz demo, because a new standard can take two years of work, he said. Though Rambus is getting design wins for its chip-stacking approach in Motorola Razr phones, Wide I/O is perhaps 3-5 years away from significant market use. "FPGAs have demoed [Wide I/O memory], but high-volume systems will stay with separately packaged DRAMs for a while because of test, packaging, and business issues and logistics."

Having gotten its letter of acceptance from Jedec today, Rambus expects to participate at the next meeting, probably in June.

Rambus left Jedec in about 1996 amid controversy over its RDRAM technology. At the height of litigation, it was involved in suits with as many as 15 memory companies over DRAM patents. Some memory companies claimed Rambus violated Jedec rules by patenting technologies discussed at standards meetings. Rambus denied the charge.

In recent years, Rambus has worked to settle the suits. The last one -- with Micron -- started in 2000 and was settled in December.

"We changed the company a lot in management and engagement with industry," Donnelly said. "We have resolved all the litigation that was outstanding, and we are engaged with all the memory guys."

By: DocMemory
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