NVMe is now supported by 90+ leading companies and a 30-company promoter group. The first products began shipping in 2014. The driving force for NVMe acceptance is its ability to move NV memory from the legacy of the rotating disc and serial operation to parallel operation. Standardization of the register, feature, and command sets is a means of moving from proprietary to product interoperability.

Flash memory multilevel cell (MLC) NAND provides the primary non-volatile part of the present proof of performance of NVMe-based designs, which is impressive. The appearance of emerging NV memories would appear to hold the key to a dramatic factor of 4x improvement in future performance. However, the saving grace is NVMe has been designed to be memory independent or “agnostic” to the memory technology that eventually wins the NV emerging technology race.

This writer hoped this Tech Talk would provide some insight into Intel's viewpoint as to which of the competing technologies might win the emerging NV memory race and, more importantly, the timing of its emergence -- even though, as stated earlier, the NVMe controller has been designed on a “don't care” basis in that respect.

Huffman's list of emerging memory types is shown in my Figure 1. It included the usual suspects with a brief description of the mechanisms involved. The list included as mechanisms: phase change, spin polarized electrons, electro-chemistry, oxidation-reduction, and oxygen vacancy drift diffusion and barrier modulation.

What was interesting is that a multilayer stacked memory matrix (see Figure 1) was used for illustrative purposes rather than one that was MLC based. In the past, Intel, with STMicroelectronics and, more recently, at IEDM 2009 with Numonyx, has looked at and demonstrated both multilevel cell (MLC-PCM) and stacked matrix, albeit the latter only a single-layer matrix where the thin-film memory isolation or selection device is stacked vertically above the memory device. As far as we are aware, those projects have disappeared into the PCM technology amortization trail of Intel-STMicroelectronics-Ovonyx-Numonyx-Micron.

It could well be that Intel recognizes that a stacked array may offer the only solution to any scaling problems, especially as Huffman included the word “scalable” in her slides referring to next-generation NVM. The development of a stacked thin-film matrix isolation device is a non-trivial problem that will require a solution before the next generation of multilayer NV memory can emerge.

This list in Figure 1 omits correlated electron memory devices, although oxidation-reduction might cover one case. CeRAM, without the filament; and, more recently, the change in tack to correlated electron device for the group developing PCMO-based memory will cover the other under both the oxidation reduction and modulated interface banners.

Huffman specifically mentioned only MRAM as an example of an emerging NV memory. A followup question by this writer inquiring if that is Intel's view of the most likely near-term emerging NV technology winner was rebuffed with a reply along the lines of: Intel does not wish to comment on emerging memory technologies or which one will win.

Figure 2 provides Huffman's comparative performance of the NVMe illustrating the dramatic gains that will be obtained when emerging NV memory eventually reaches maturity and is able to offer the access times comparable with today's DRAMs.

By: DocMemory
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