A Tokyo Institute of Technology (TIT) research has yielded a technology for the ultra-thinning process down to 4µm.

In collaboration with DISCO Corporation, Fujitsu Laboratories Ltd, PEZY Computing, and the WOW Alliance, TIT Professor Takayuki Ohba has implemented the process using a 300mm 2G bit DRAM memory.

It was confirmed that there were no changes in the probability failure rate of refresh times before and after thinning-down, which means no new atomic defects occurred due to the thinning process.

The ultra-thinning process was carried out by the bumpless WOW 3D process—3D integration technology for making large-scale integrated circuits by wafer stack (wafer-on-wafer). There is stack methods including chip-on-chip and chip-on-wafer and productivity increased in the order of COCUsing these thinned wafers, the length of the wiring between upper- and lower-layer chips is reduced to below 1/10 compared to conventional TSVs, with wiring resistance, capacitance, and volume being reduced drastically. It is expected to realise applications in ultra-small, Terabit-generation large-scale memory.

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved