The early access design software developed by Altera Corporation for Stratix 10 FPGAs and SoCs is the industry's first design software that targets 14nm FPGAs. Design engineers can start their Stratix 10 designs and experience first-hand the 2X core performance gains they can achieve as a result of the Stratix 10 HyperFlex architecture and the Intel 14nm Tri-Gate process.

With this design software, Altera introduces the Hyper-Aware design flow, which includes the innovative Fast Forward Compilation (FFC) capability that allows customers to perform rapid design performance exploration and attain breakthrough levels of performance.

With the breakthrough leap in core performance that Stratix 10 FPGAs deliver, users are now able to unlock the performance in their designs by taking advantage of the innovative capabilities of the HyperFlex architecture to reach levels of performance not possible in previous generation FPGA architectures.

Developed to enable 2X performance in a customer's design, FFC pinpoints performance bottlenecks and provides detailed, step-by-step performance improvement recommendations that a user can rapidly implement.

Users also receive Fmax (maximum operating frequency) estimates of their design that can be achieved by applying the recommendations FFC provides. With this innovative design flow, FFC gives customers an opportunity to maximise overall design performance made possible by Stratix 10 FPGAs and SoCs and achieve rapid timing closure.

Previously, in order to achieve high-performance targets, users often needed to undergo multiple, time-consuming design iterations, including trying various design optimisations and re-running full FPGA compiles to determine the effectiveness of design changes. With FFC, users receive detailed guidance for design optimisation and an estimated design Fmax to leverage the HyperFlex architecture.

With these insights, customers are better able to make decisions for where to most effectively invest development time to increase their design's performance and throughput, taking the guesswork out of performance exploration. As a result, Stratix 10 FPGA and SoC customers perform fewer design iteration cycles to achieve their performance targets and simplify the path to achieving 2X core performance gains.

By: DocMemory
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